F75111 Datasheet, PDF (35/45 Pages) Feature Integration Technology Inc. – Low Power GPIO Datasheet

7.43 GPIO3x Level/Pulse Control Register – Index 43h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-4 Reserved
RO VSB3V Read back will be zero
3
GP33_OMODE R/W VSB3V GPIO 33 output mode. 0 – level, 1 – pulse.
2
GP32_OMODE R/W VSB3V GPIO 32 output mode. 0 – level, 1 – pulse.
1
GP31_OMODE R/W VSB3V GPIO 31 output mode. 0 – level, 1 – pulse.
0
GP30_OMODE R/W VSB3V GPIO 30 output mode. 0 – level, 1 – pulse.
F75111
7.44 GPIO3x Pulse Width Control Register – Index 44h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7:2 Reserved
R/W VSB3V Reserved. Read return 0.
1:0 GP3_PLSWD[1:0 R/W VSB3V GPIO3x pulse width. If set the GPIO3x to pulse mode, the pulse width
]
can be defined as follows.
00b – 500us (Default)
01b – 1ms
10b – 20ms
11b – 100ms
7.45 GPIO3x Input De-bounce Register – Index 46h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7-4 Reserved
RO VSB3V Read back will be zero
3
GP33_ENDB R/W VSB3V Enable GPIO33 input de-bounce with 7u or 25ms second that selected
by 0x4C bit3.
2
GP32_ENDB R/W VSB3V Enable GPIO32 input de-bounce with 7u or 25ms second that selected
by 0x4C bit2.
1
GP31_ENDB R/W VSB3V Enable GPIO31 input de-bounce with 7u or 25ms second that selected
by 0x4C bit1.
0
GP30_ENDB R/W VSB3V Enable GPIO30 input de-bounce with 7u or 25ms second that selected
by 0x4C bit0.
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July, 2007
V0.27P