F75111 Datasheet, PDF (11/45 Pages) Feature Integration Technology Inc. – Low Power GPIO Datasheet

F75111
SCL
SDA
0
780
78
1
Start By
Master
00111
Frame 1
Serial Bus Address Byte
0 R/W
Ack
by
111
0
D7 D6 D5 D4 D3 D2 D1 D0
Frame 2
Internal Index Register Byte
Ack Stop by
by
Master
111
Figure 2. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
SCL
SDA
0
780
78
1
Start By
Master
00111
Frame 1
Serial Bus Address Byte
0 R/W
Ack
by
111
0
D7 D6 D5 D4 D3 D2 D1 D0
Frame 2
Internal Index Register Byte
Ack
by Stop by
Master ^Master
Figure 3. Serial Bus Read from Internal Address Register
7. Registers Description
7.1 Configuration and Control Register – Index 01h
Power-on default [7:0] =0000_1000b
Bit
Name
7
INIT
6
Reserved
R/W
R/W
R/W
PWR
VSB3V
VSB3V
Description
Software reset for all registers including Test Mode registers. Users use
only.
5
EN_WDT10
R/W VSB3V Enable Reset Out. If set to 1, enable WDTOUT10# output. Default is
disable.
4
Reserved
R/W VSB3V
3
Reserved
R/W VSB3V
2
Reserved
R/W VSB3V
1
SMART_POW R/W VSB3V Set this bit to 1 will enable auto power down mode, when all function are
R_MANAGEM
idle then 20ms the chip will auto power down, it will wakeup when GPIO
ENT
state change or read write register
0
SOFT_POWR_ R/W VSB3V Set this bit to 1 will power down all of the analog block and stop internal
DOWN
clock, write 0 to clear this bit or when GPIO state change will auto clear
this bit to 0.
-9-
July, 2007
V0.27P