F75111 Datasheet, PDF (19/45 Pages) Feature Integration Technology Inc. – Low Power GPIO Datasheet

6
GP16_PSTS RO VSB3V Read the GPIO16 data on the pin.
5
GP15_PSTS RO VSB3V Read the GPIO15 data on the pin.
4
GP14_PSTS RO VSB3V Read the GPIO14 data on the pin.
3
GP13_PSTS RO VSB3V Read the GPIO13 data on the pin.
2
GP12_PSTS RO VSB3V Read the GPIO12 data on the pin.
1
GP11_PSTS RO VSB3V Read the GPIO11 data on the pin.
0
GP10_PSTS RO VSB3V Read the GPIO10 data on the pin.
F75111
7.13 GPIO1x Level/Pulse Control Register – Index 13h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7
GP17_OMODE R/W VSB3V GPIO 17 output mode. 0 – level, 1 – pulse.
6
GP16_OMODE R/W VSB3V GPIO 16 output mode. 0 – level, 1 – pulse.
5
GP15_OMODE R/W VSB3V GPIO 15 output mode. 0 – level, 1 – pulse.
4
GP14_OMODE R/W VSB3V GPIO 14 output mode. 0 – level, 1 – pulse.
3
GP13_OMODE R/W VSB3V GPIO 13 output mode. 0 – level, 1 – pulse.
2
GP12_OMODE R/W VSB3V GPIO 12 output mode. 0 – level, 1 – pulse. If this serves as IRQ/SMI#
mode, it will have same function.
1
GP11_OMODE R/W VSB3V GPIO 11 output mode. 0 – level, 1 – pulse.
0
GP10_OMODE R/W VSB3V GPIO 10 output mode. 0 – level, 1 – pulse.
7.14 GPIO1x Pulse Width Control Register – Index 14h
Power-on default [7:0] =0000_0000b
Bit
Name
R/W PWR
Description
7:2 Reserved
R/W VSB3V Reserved. Read return 0.
1:0 GP1_PSWDTH[1:0 R/W VSB3V GPIO1x pulse width. If set the GPIO1x to pulse mode, the pulse
]
width can be defined as follows.
00b – 500us (Default)
01b – 1ms
10b – 20ms
11b – 100ms
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July, 2007
V0.27P