FMS9874 Datasheet, PDF (6/25 Pages) Fairchild Semiconductor – Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps

PRODUCT SPECIFICATION
Name
PLLCTRL
CONFIG 2
Address
0C
0D
0E
0F
Function
PLL Control
Configuration Register No. 2
Reserved
Reserved
FMS9874
Default (hex)
24
00
0X
00
Register Definitions
Configuration Register 1 (0A)
Bit no.
0
1
2
3
4
5
6
7
Name
XCKSEL
XCLAMPOL
XCLAMP
COASTPOL
HSPOL
—
—
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
External Clock Select. Select internal clock source.
0: Internal PLL
1: XCK input.
External Clamp Polarity. Select clamp polarity.
0: Active L.
1: Active H.
External Clamp Select. Select clamp source.
0: Internally generated by PLL referenced to HSIN.
1: External CLAMP input.
Coast Polarity. Select COAST input polarity.
0: Active L.
1: Active H.
HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected
edge:
0: Falling edge.
1: Rising edge.
0: Default must be 0.
0: Default must be 0.
PLL Configuration Register (0C)
Bit no.
Name
Type Description
1-0
—
4-2
IPUMP_2-0 R/W Charge Pump Current. Selects Charge Pump current (µA). (see Table 5.
Charge Pump Current Codes)
000: 50
001: 100
010: 150
011: 250
100: 350
101: 500
110: 750
111: 1500
6-5
FVCO_1-0 R/W VCO Frequency Range. Selects VCO frequency range (MHz).
00: 20–90
01: 20–90
10: 80–108
11: —
7
—
R/W Reserved.
0: Run.
1: (reserved).
6
REV. 1.5 11/10/00