FMS9874 Datasheet, PDF (21/25 Pages) Fairchild Semiconductor – Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps

FMS9874
PRODUCT SPECIFICATION
Applications Information
To minimize component count, use of the following on-chip
circuits is recommended:
1. ADC sampling clock.
2. Clamp.
3. Voltage reference
Optimum PLL Configuration Register (address 0x0C) set-
tings for typical graphics modes are listed in Table 3. Unless
otherwise indicated, all modes are compliant with VESA
specifications. For unlisted modes, values should be adjusted
to optimize performance.
By adjusting the values in the gain (GR, GG, GB) and offset
(OSR, OSG, OSB) registers, the input conversion range can
be matched to the incoming analog signals.
AC Coupled Digitizer
Shown in Figure 22 is an implementation of a video digitizer
with AC coupled RGB inputs. Horizontal sync input, HS is
passed through a voltage divider which attenuates the 5.0 V
logic HIGH excursion to the 3.3 V HIGH input level of the
FMS9874. Vertical sync is also attenuated to make the
VSOUT level compatible with 3.3 V pixel processing
following the FMS9874.
Output data is three channel 24-bit pixels with a maximum
rate of 140Ms/s. Data is clocked out on the negative edge of
DCK. HSOUT defines the active video along a line, while
incoming vertical sync, VSIN is propagated as VSOUT to
the output data to synchronize handling of digitized frames
of output data.
Control is through the serial port with 150Ω resistors
inserted to allow interfacing with 5V logic. If the serial bus is
operates with 3.3V levels, these resistors are unnecessary.
1
2
RED
GREEN
3
BLUE
4
C2
.047µF
5
6
C3
7
.047µF
R2
8
9
R3
75
75
10
11
12
13
14
15
R4
VDDP
1K
C1
0.18µF
R1
1.5K
C4
0.018µF
R5
1.8K
SCL
SDA
COAST
C1
.047µF
VDDP
VDDA
R1
75
VDD
R7
10K
C8
0.1µF
U1
FMS9874
24
25
31
36
38
VDDP
VDDP
VDDP
VDDP
VDDP
2 _RIN
8 _GIN
13 _BIN
18 _INVSCK
19 _CLAMP
28 _HSIN
29 _COAST
32 _XCK
33 _LPF
20 _SDA
21 _SCL
22 _A0
23 _A1
7 _ACSIN
73
74
75
NC9
NC10
NC11
98 _VREFIN
96 _PWRDN
97 _VREFOUT
VDDO
DB7 ⁵¹
DB6 ⁵²
DB5 ⁵³
DB4
DB3
DB2
DB1
DB0
54
55
56
57
58
DG7
DG6
DG5
DG4
DG3
DG2
DG1
DG0
63
64
65
66
67
68
69
70
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
76
77
78
79
80
81
82
83
DCK ⁸⁶
DCK ⁸⁷
HSOUT ⁸⁸
DCSOUT ⁸⁹
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
34
42
43
44
45
46
47
48
BA7
BA6
BA5
BA4
BA3
BA2
BA1
BA0
GA7
GA6
GA5
GA4
GA3
GA2
GA1
GA0
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
BA[7..0]
GA[7..0]
RA[7..0]
DCK
DCK
HSOUT
Figure 22. Schematic, VGA Digitizer, AC Coupled RGB
VSOUT
REV. 1.5 11/10/00
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