FMS9874 Datasheet, PDF (4/25 Pages) Fairchild Semiconductor – Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps

PRODUCT SPECIFICATION
FMS9874
Pin Descriptions
Pin Name Pin No.
Converter Channels
R_IN, G_IN, B_IN 2, 8, 13
DR_7-0
76–83
DG_7-0
63–70
DB_7-0
51–58
Timing Generator
CLAMP
19
INVSCK
18
XCK
32
DCK
86
DCK
87
HSOUT
88
Phase Locked Loop
HSIN
28
COAST
29
LPF
33
Sync Stripper
ACS_IN
7
DCS_OUT
89
Control
SDA
20
SCL
21
A₀
22
A₁
23
PWRDN
96
Type/Value Pin Function Description
Input
Output
Output
Output
Analog Inputs.
Red Channel A Data Output.
Green Channel A Data Output.
Blue Channel A Data Output.
Input
Input
Input
Output
Output
Output
External Clamp Input.
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 216Ms/s.
External Clock input. Enabled if register bit, XCKSEL = H. Replaces
PXCK clock generated by PLL. If unused, connect to ground through a
10kΩ resistor.
Output Data Clock. Clock for strobing output data to external logic.
Output Data Clock Inverted. Inverted clock for strobing output data to
external logic.
Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9874 latency and synchronized with DCK. Leading edge is
synchronized to start of data output. Polarity is always active HIGH.
Schmitt
Input
Passive
Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source
should be clamped at 3.3V or current limited to prevent overdriving
ESD protection diodes.
PLL Coast. Maintain frequency of PLL output clock PXCK,
disregarding HSIN. If horizontal sync is missing during the vertical sync
interval, PXCK clock frequency can be maintained by asserting
COAST.
PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Figure 13.)
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
Digital Composite Sync Output. Output from sync stripper.
Bi-directional Serial Port Data. Bi-directional data.
Input
Serial Port Clock. Clock input.
Input
Address bit 0. Lower bit of serial port address.
Input
Address bit 1. Upper bit of serial port address.
Input
Power Down/Output Control. Powers down the FMS9874 and
tri-states the outputs.
4
REV. 1.5 11/10/00