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FMS9874 Datasheet, PDF (5/25 Pages) Fairchild Semiconductor – Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps
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PRODUCT SPECIFICATION
FMS9874
Pin Descriptions
Pin
Name
Pin No.
Pin Function Description
Power and Ground
VDDA
VDDP
3, 5, 9, 11, 14, 16, 95, 99, 100 ADC Supply Voltages. Provide a quiet noise free voltage.
24, 25, 31, 36, 38
PLL Supply Voltage. Most sensitive supply voltage. Provide a very
quiet noise free voltage.
VDDO
50, 60, 62, 72, 85, 91
Digital Output Supply Voltage. Decouple judiciously to avoid
propagation of switching noise.
GND
1, 4, 6, 10, 12, 15, 17, 26, 27, Ground. Returns for all power supplies. Connect ground pins to a
30, 35, 37, 39, 40, 41, 49, 59, solid ground plane.
61, 71, 84, 90, 92, 93, 94
VREFIN
98
Voltage Reference Input. Common reference input to RGB
converters. Connect to VREFOUT, if internal reference is used.
VREFOUT
97
Voltage Reference Output. Internal band-gap reference output. Tie to
ground through a 0.1µF capacitor.
Addressable Memory
Register Map
Name
PLLN11-4
PLLN3-0
GR7-0
GG7-0
GB7-0
OSR5-0
OSG5-0
OSB5-0
CD7-0
CW7-0
CONFIG 1
PHASE7-0
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
Function
PLL divide ratio, MSBs. PLLN + 1 = total number of
pixels per horizontal line.
PLL divide ratio, LSBs. PLLN + 1 = total number of pixels
per horizontal line. PLLN3-0 stored in the four upper
register bits 7-4.
PLLN3–0 X X X X
Gain, red channel. Adjustable from 70 to 140%.
Gain, green channel. Adjustable from 70 to 140%.
Gain, blue channel. Adjustable from 70 to 140%.
Offset, red channel. OSR5-0 stored in the six upper
register bits 7-2.Default value is decimal 32.
OSR5–0
XX
Offset, green channel. OSR5-0 stored in the six upper
register bits 7-2. Default value is decimal 32.
OSG5–0
XX
Offset, blue channel. OSR5-0 stored in the six upper
register bits 7-2. Default value is decimal 32.
OSB5–0
XX
Clamp delay. Delay in pixels from trailing edge of
horizontal sync.
Clamp width. Width of clamp pulse in pixels.
Configuration Register No. 1
Sampling clock phase. PHASE4-0 stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25° increments. Default value is decimal 16.
PHASE4–0 X X X
Default (hex)
69 (1693)
D0 (1693)
80
80
80
80
80
80
80
80
F4
10
5
REV. 1.5 11/10/00
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