FMS9874 Datasheet, PDF (13/25 Pages) Fairchild Semiconductor – Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps

FMS9874
PRODUCT SPECIFICATION
Table 3. Recommended IPUMP and FVCO values for Standard Display Formats¹ (continued)
Standard
XGA
SXGA
Resolution
1024 X 768
1280 X 1024
Refresh Rate
60 Hz
70 Hz
75 Hz
80 Hz
85 Hz
60 Hz
Horizontal
Frequency
48.4 kHz
56.5 kHz
60.0 kHz
64.0 kHz
68.3 kHz
64.0 kHz
Sample Rate
65.000 MHz
75.000 MHz
78.750 MHz
85.500 MHz
94.500 MHz
108.000 MHz
FVCO_1-0
01
01
10
10
Notes:
1. VESA Monitor Timing Standards and Guidelines, September 17, 1998 and others.
IPUMP_2-0
111
111
111
111
C1
0.18µF
R1
1.5K
VDDP
C2
0.018µF
LPF
Figure 16. Schematic, PLL Filter.
Loop performance is established by setting:
1. VCO frequency range through FVCO_1-0. (see Table 4)
2. Charge Pump Current through IPUMP_2-0. (see Table 5)
3. External loop filter component values.
Table 4. VCO Frequency Bands
FVCO_2-0
00
01
Frequency Range (MHz) KVCO (MHz/V)
20–90
60
10
75–108
90
11
—
—
Table 5. Charge Pump Current Levels
IPUMP_2-0
000
001
010
011
100
101
110
111
Current (µA)
50
100
150
250
350
500
750
1500
Setting SPHASE_4-0 selects the sampling phase of SCK rela-
tive to PXCK in 32 steps of 11.25°. Phase of the output data,
DCK and DCK is slaved to the SCK phase.
COAST = H disables PLL lock to HSIN, while the VCO
frequency is retained. VCO frequency remains stable over
several lines without updates from HSIN. COAST can be
connected directly to the vertical sync signal or supplied by
the graphics controller.
RMS Clock jitter is less than 3% of pixel period in all operat-
ing modes. At lower frequencies below 40MHz, the jitter
rises but can be reduced by over-sampling at a 2X clock rate.
See Performance section for jitter specifications and plots.
COAST
COAST = H disables PLL lock to HSIN, while the VCO
frequency is retained. VCO frequency remains stable over
several lines without updates from HSIN. COAST can be
connected directly to the vertical sync signal or supplied by
the graphics controller.
Operation of COAST is depicted in Figure 17. HSOUT
polarity is always positive. When COAST = L, HSOUT
tracks HSIN (shown with postive polarity in Figure 1 ):
1. HSOUT rising edge tracks HSIN delayed by a few pixels.
2. HSOUT falling edge tracks the trailing edge of HSIN
with no delay.
When COAST = H, the PLL flywheels, disregarding the
incoming HSIN references, while the HSOUT waveform
depends upon the state of HSIN.
1. If HSIN = H:
a.) HSOUT rising edge remains locked to the PLL.
b.) HSOUT trailing edge falls after 50% of the HSOUT
period has expired.
2. HSIN transitions:
a.) HSOUT rising edge remains locked to the PLL.
b.) HSOUT falling edge is terminated by the trailing
edge of HSIN.
3. If HSIN = L, then HSOUT = L
REV. 1.5 11/10/00
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