FMS9874 Datasheet, PDF (14/25 Pages) Fairchild Semiconductor – Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps

PRODUCT SPECIFICATION
HSIN
COAST
HSOUT
FMS9874
Trailing edge terminates HSOUT
50% Timeout
Figure 17.
Timing Generator
Timing and Control logic generates:
1. Internal sampling clock, SCK.
2. Output data clocks, DCK and DCK.
3. Output horizontal sync, HS_OUT.
4. Internal clamp pulse, ICLAMP.
With HSPOL set correctly, ICLAMP delay follows the trail-
ing edge of horizontal sync in (HSIN). Delay is set by the
CD register. Width of ICLAMP is set by the CW register.
Range of CD and CW values is 1–255 pixels.
Sync Stripper
Some video signals include embedded composite sync rather
than separate horizontal and vertical sync signals, typically
sync on green. Composite sync is extracted from Composite
Video at the ACS_IN pin.
When the ACS_IN signal falls below a 150mV ground refer-
enced threshold, sync is detected. Composite Sync Output,
DCS_OUT reflects the ACS_IN sync timing with non-inverted
CMOS digital levels.
Power Down
PWRDN = L minimizes FMS9874 power consumption.
Data outputs become high impedance. Clocks generation is
stopped. Register contents are maintained. Sync stripping
and the internal voltage reference function.
Serial Interface
Register access is via a 2-wire I²C/SMBus compatible inter-
face. As a slave device, the 7-bit address is selected by the
A_1-0 pins (see Table 6). Serial port pins SDA and SCL com-
municate with the host SMBus/I²C controller which act as a
master.
Since the serial control port is design to interface with 3.3V
logic, the pins must be protected by series connected 150Ω
resistors if SDA and SCL signals originate from 5V logic.
(See Applications Section)
Table 6. Serial Interface Address Codes
A_1-0
7-Bit Address
00
4C
01
4D
10
4E
11
4F
Two signals comprise the bus: clock (SCL) and bi-directional
data (SDA). When receiving and transmitting data through
the serial interface, the FMS9874 acts as a slave, responding
only to commands by the I²C/SMBus master.
Data received or transmitted on the SDA line must be stable
for the duration of the positive-going SCL pulse. Data on
SDA may change only when SCL = L. An SDA transition
while SCL = H is interpreted as a start or stop signal.
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