FMS9874 Datasheet, PDF (22/25 Pages) Fairchild Semiconductor – Graphics Digitizer - 3x8-Bit, 108Ms/s Triple Video A/D Converter with Clamps

PRODUCT SPECIFICATION
FMS9874
Printed Wiring Board Design Guidelines
Recommended strategy is to mount the FMS9874 over a
ground plane with carefully routed analog inputs and digital
outputs. All connections should be treated as transmission
lines to ensure that reflections due to mismatches are mini-
mized and ground return currents do not interfere with critical
signals.
Analog Inputs
Recommendations:
1. Keep analog trace lengths short to minimize crosstalk.
2. Terminate analog inputs with 75Ω resistors, placed
close to the FMS9874 analog inputs, R_IN, G_IN and B_IN.
By matching transmission line impedances, reflections
will be minimized.
3. Layout traces as 75Ω transmission lines.
4. Avoid running analog traces near digital traces. Due to
the wide input bandwidth (500MHz) digital noise can
easily leak into analog inputs.
5. If necessary, limit bandwidth by adding a ferrite bead in
series with each RGB input as shown in Figure 23. A
Fair-Rite #2508051217Z0 is recommended. Further
bandwidth reduction using a shunt 10pF capacitor may
reduce snow (intensity noise) caused by HF noise riding
on the RGB input. Mismatches, reflections and noise
may cause ringing or distortion of the incoming video
signals.
6. Locate the PLL filter clear of other signals.
7. Bypass the reference with a 0.1µF capacitor to ground.
R,G, B INPUT
L1
BEAD
C1
47nF
R_IN, G_IN, B_IN
R1
C2
75
10pF
Digital I/O
Recommendations:
1. Route digital I/O signals clear of analog inputs.
2. Terminate clock lines to reduce reflections. Treat clock
lines as transmission lines.
3. Scale the HSIN input to 3.3V, using a resistor network
or a series 1 kΩ resistor.
4. Limit Serial Port inputs SDA and SDL with 150Ω resis-
tors connected directly to the pins.
5. If necessary terminate the HSIN input with 330/220Ω.
6. If necessary, to reduce reflections, EMI or spikes add a
50–200Ω resistor at each data output pin.
7. To minimize noise within the FMS9884A, restrict the
capacitive load at the digital outputs to < 10pF.
Power and Ground
A schematic of the recommended power distribution is
shown in Figure 24. Note that:
1. Analog and digital circuits are layed out over a common
solid ground plane.
2. Each FMS9874 pin is decoupled with a 0.1µF capacitor.
3. A group of pins may be de-coupled through a common
capacitor if no pin is more than 5 mm from the capacitor.
4. A separate regulated supply is used for the phase-locked
loop power supply, V_DDP.
5. Capacitors are attached to each PLL pin or pin-pair.
Figure 23. RGB Input Filter Option
22
REV. 1.5 11/10/00