FAN6921ML Datasheet, PDF (5/23 Pages) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

Pin Definitions
Pin # Name Description
Input to the comparator of the PWM over-current protection and performs PWM current-mode
control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch
5 CSPWM and the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, current-
mode control, and high / low line over-power compensation according to DET pin source current
during PWM on time.
6
OPFC
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is
15.5V.
7
VDD
Power supply. The threshold voltages for startup and turn-off are 18V and 7.5V, respectively. The
startup current is less than 30µA and the operating current is lower than 10mA.
8
OPWM
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
gate output voltage is 17.5V.
9
GND The power ground and signal ground.
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
ƒ Producing an offset voltage to compensate the threshold voltage of PWM current limit for
providing over-power compensation. The offset is generated in accordance with the input
voltage when PWM switch is on.
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DET ^{ƒ Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley}
voltage switching and minimize the switching loss on the PWM switch.
ƒ Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
OVP and this flat voltage is higher than 2.5V, the controller enters latch mode and stops all PFC
and PWM switching operation.
Feedback voltage pin. This pin is used to receive the output voltage level signal to determine PWM
gate duty for regulating output voltage. The FB pin voltage can also activate open-loop, overload,
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FB or output-short-circuit protection if the FB pin voltage is higher than a threshold of around 4.2V for
more than 50ms.The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator is
connected between the FB pin and the input of the CSPWM/FB comparator.
Adjustable over-temperature protection and external latch triggering. A constant current flows out
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RT of the RT pin. When RT pin voltage is lower than 0.8V (typical), latch mode protection is activated
and stops all PFC and PWM switching operation until the AC plug is removed.
Line-voltage detection for brownin/out protections. This pin can receive the AC input voltage level
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VIN through a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin’s
status, but it can also perform brownin/out protection for AC input voltage UVP.
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
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ZCD
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle.
When the ZCD pin voltage is pulled to under 0.2V (typical), it disables the PFC stage and the
controller stops PFC switching. This can be realized with an external circuit if disabling the PFC
stage is desired.
15
NC No connection
16
HV
High-voltage startup. HV pin is connected to the AC line voltage through a resistor (100kΩ typical)
for providing a high-charging current to VDD capacitor.
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
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