FAN6921ML Datasheet, PDF (3/23 Pages) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

Internal Block Diagram
COMP
HV
VDD
INV
CSPFC
FB
CSPWM
DET
2
RANGE
2.65V
Multi-Vector Amp.
2.75V
RANGE
2.75V
2.9V
2.3V
0.45V
16
7
IHV
OVP
27.5V
OVP
Latched
Two Steps
UVLO
18V/10V/7.5V
UVP
Debounce
70µs
3
Latched
Brownout
S ^SET Q
R CLR Q
Internal
Bias
15 NC
DRV
15.5V
6 OPFC
4
11
2.5V
THD
Optimizer
Blanking
Circuit
0.6V
PFC
Current Limit
VCTL-PFC-ON/OFF
Debounce
550ms / 150µs
Soft-Start
9.5ms
4.2V
2R
R
Timer
50ms
2.5ms
VB
32.5µs
Starter
Sawtooth
Generator
/tON-MAX-PFC
Restarter
Disable
Function
0.2V
Inhibit
Timer
VC & PFC ON/OFF &
Multi Vector Amp.
ON/OFF
0.7V
PFC Zero Current
Detector
2.1V/1.75V
14
10V
IZCD
FB OLP
DRV
S ^SET Q
8
Blanking
5
Circuit
R CLR Q
17.5V
Over Power
Compensation
PWM
Current Limit
IDET
DET pin OVP
VDD pin OVP
Internal OTP
tOFF-MIN
IDET
Valley
(8us/37µs/2.5ms)
Detector
1^st Valley
tOFF-MIN
+9µs
(RT Pin) Prog. OTP
Brownout
Protection
(RT Pin) Externally Triggering
Output Short Circuit (FB
Latched
Pin)
Output Open-Loop (FB Pin)
Output Over Power/ Overload (FB Pin)
Lathed
Protection
tOFF
Blanking
(4µs)
VDET
S/H
2.5V
Latched
DET OVP
VC
Latched
Debounce
Time
Startup
VB & clamp
1
VCOMP to 1.6V
10
0.3V
IRT
100uA
0.8V
1.2V
0.8V VINV ^VINV
Brownout
Debounce
100ms
5V
IDET
1V/1.2V
comparator
Debounce
100ms
100us
Internal
OTP
Latched
0.5V
10ms
Prog. OTP
2.35V/2.15V
9
/ Externally Triggering
12
13
PFC RANGE Control
ZCD
OPWM
RANGE
GND
RT
VIN
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
3
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