FAN6921ML Datasheet, PDF (19/23 Pages) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

Figure 39. Valley Detection
As the input voltage increases, the reflected voltage on
the auxiliary winding, VAUX, becomes higher (as well as
the current IDET) and the controller regulates the VLIMIT to
a lower level.
The RDET resistor is connected from auxiliary winding to
the DET pin. Engineers can adjust this RDET resistor to
get proper VLIMIT voltage to fit power system needs. The
characteristic curve of IDET current vs. VLIMIT voltage on
CSPWM pin is shown in Figure 42.
( ) I_DET = ⎡⎣V_IN × N_A N_P ⎤⎦ R_DET
(1)
where VIN is input voltage; NA is turn number of auxiliary
winding; and NP is turn number of primary winding.
Figure 40. Measured Waveform of Valley Detection
High / Low Line Over-Power Compensation (DET Pin)
Generally, when the power switch turns off, there is a
delay from gate signal falling edge to power switch off.
This delay is produced by an internal propagation delay
of the controller and the turn-off delay of the PWM
switch due to gate resistor and gate-source capacitor
CISS of PWM switch. At different AC input voltage, this
delay time produces different maximum output power
under the same PWM current limit level. Higher input
voltage generates higher maximum output power since
applied voltage on primary winding is higher and causes
higher rising slope inductor current. It results in higher
peak inductor current at the same delay. Furthermore,
under the same output wattage, the peak switching
current at high line is lower than at low line. Therefore,
to make the maximum output power close at different
input voltages, the controller needs to regulate VLIMIT of
the CSPWM pin to control the PWM switch current.
Referring to Figure 41, during the on time of the PWM
switch, the input voltage is applied to primary winding
and the voltage across on auxiliary winding, VAUX, is
proportional to primary winding voltage. As the input
voltage increases, the reflected voltage on auxiliary
winding VAUX rises as well. FAN6921ML also clamps the
DET pin voltage and flows out a current IDET. Since the
current, IDET, is in accordance with VAUX, FAN6921ML
can depend on this current IDET during PWM on time to
regulate the current limit level of the PWM switch to
perform high / low line over-power compensation.
Figure 41. Relationship between VAUX and VIN
Figure 42. IDET Current vs. VLIMIT Voltage
Characteristic Curve
Leading-Edge Blanking (LEB)
When the PFC or PWM switches are turned on, a
voltage spike is induced on the current-sense resistor
due to the reciprocal effect by reverse recovery energy
of the output diode and COSS of power MOSFET. To
prevent this spike, a leading-edge blanking time is built-
in and a small RC filter is recommended between the
CSPWM pin and GND (e.g. 100Ω, 470pF).
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
19
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