FAN6921ML Datasheet, PDF (11/23 Pages) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

Electrical Characteristics (Continued)
VDD=15V, TA=-40℃~105℃ (TA=TJ), unless otherwise specified.
Symbol
Parameter
Conditions
PWM Output Section
VCLAMP
PWM Gate Output Clamping
Voltage
VDD= 25V
VOL
PWM Gate Output Voltage Low
VOH
PWM Gate Output Voltage High
tR
PWM Gate Output Rising Time
tF
PWM Gate Output Falling Time
Current Sense Section
VDD= 15V, Io=100mA
VDD= 15V, Io=100mA
CL=3nF,
VDD=12V, 20~80%
CL=3nF,
VDD=12V, 20~80%
tPD
VLIMIT
Delay to Output
The Limit Voltage on CSPWM
Pin for Over Power
Compensation
VSLOPE
Slope Compensation⁽⁴⁾
tON-BNK
VCS-FLOATING
Leading-Edge Blanking Time
CSPWM Pin Floating VCSPWM
Clamped High Voltage
IDET < 75µA, TA=25°C
IDET=185µA, TA=25°C
IDET=350µA, TA=25°C
IDET=550µA, TA=25°C
tON=45µs,
RANGE=Open
tON=0µs
CSPWM Pin Floating
tCS-H
Delay Once CSPWM Pin Floating CSPWM Pin Floating
RT Pin Over-Temperature Protection Section
TOTP
Internal Threshold Temperature
for OTP⁽⁴⁾
TOTP-HYST
Hysteresis Temperature for
Internal OTP⁽⁴⁾
IRT
VRT-LATCH
Internal Source Current of RT Pin
Latch-Mode Triggering Voltage
VRT-RE-LATCH Latch-Mode Release Voltage
VRT-OTP-LEVEL
Threshold Voltage for Two-level
Debounce Time
tRT-OTP-H Debounce Time for OTP
tRT-OTP-L
Debounce Time for Externally
Triggering
Note:
4. Guaranteed by design.
VRT<VRT-OTP-LEVEL
Min. Typ. Max.
16.0
17.5
19.0
1.5
8
80
110
40
70
150
200
0.81
0.84
0.87
0.69
0.72
0.75
0.55
0.58
0.61
0.37
0.40
0.43
0.25
0.30
0.35
0.05
0.10
0.15
300
4.5
5
150
125
140
155
30
90
0.75
VRT-LATCH
+0.15
100
0.80
VRT-LATCH
+0.20
110
0.85
VRT-LATCH
+0.25
0.45
0.50
0.55
10
70
100
130
Units
V
V
V
ns
ns
ns
V
V
ns
V
µs
°C
°C
µA
V
V
V
ms
µs
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
11
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