FAN6921ML Datasheet, PDF (16/23 Pages) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

RANGE Pin
A built-in low voltage MOSFET can be turned on or off
according to VVIN voltage level. The drain pin of this
internal MOSFET is connected to the RANGE pin.
Figure 29 shows the status curve of VVIN voltage level
and RANGE impedance (open or ground).
V_ZCD
10V
2.1V
1.75V
V_DS
t
PFCVO
V_IN,MAX
Figure 29. Hysteresis Behavior between RANGE Pin
and VIN Pin Voltage
Zero Current Detection (ZCD Pin)
Figure 30 shows the internal block of zero-current
detection. The detection function is performed by
sensing the information on an auxiliary winding of the
PFC inductor. Referring to Figure 31, when PFC MOS is
off, the stored energy of the PFC inductor starts to
release to the output load. Then the drain voltage of
PFC MOS starts to decrease since the PFC inductor
resonates with parasitic capacitance. Once the ZCD pin
voltage is lower than the triggering voltage (1.75V
typical), the PFC gate signal is sent again to start a new
switching cycle.
If PFC operation needs to be shut down due to
abnormal conditions, pull the ZCD pin LOW, with
voltage under 0.2V (typical), to activate the PFC disable
function to stop PFC switching operation.
For preventing excessive high switching frequency at
light load, a built-in inhibit timer is used to limit the
minimum tOFF time. Even if the ZCD signal has been
detected, the PFC gate signal is not sent during the
inhibit time (2.5µs typical).
PFC
t
Gate
Inhibit
Time
t
Figure 31. Operation Waveforms of PFC
Zero-Current Detection
Protection for PFC Stage
PFC Output Voltage UVP and OVP (INV Pin)
FAN6921ML provides several kinds of protection for the
PFC stage. PFC output over- and under-voltage are
essential for PFC stage. Both are detected and
determined by INV pin voltage, as shown in Figure 32.
When INV pin voltage is over 2.75V or under 0.45V, due
to overshoot or abnormal conditions, and lasts for a de-
bounce time around 70µs; the OVP or UVP circuit is
activated to stop PFC switching operation immediately.
The INV pin is not only used to receive and regulate
PFC output voltage, but can also perform PFC output
OVP/ UVP protection. For failure-mode test, this pin can
shut down PFC switching if pin floating occurs.
Figure 30. Internal Block of the Zero-Current
Detection
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
D riv er
Deboun ce
Time
VREF (2.5V)
COMP ^VCOMP
2
Error
C_{COMP Amplifier}
V o lt ag e
D etector
R1
INV
1
R2
OVP = (VINV ≥ 2.75V)
UVP = (V_INV ≤ 0.45V)
FAN6921
PFC V_O
C_O
Figure 32. Internal Block of PFC Over- and Under-
Voltage Protection
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