FAN6921ML Datasheet, PDF (18/23 Pages) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

PWM Stage
HV Startup and Operating Current (HV Pin)
The HV pin is connected to the AC line through a
resistor (refer to Figure 1). With a built-in high-voltage
startup circuit, when AC voltage is applied to power
system, FAN6921ML provides a high current to charge
external VDD capacitor to accelerate controller’s startup
time and build up normal rated output voltage within
three seconds. To save power consumption, after VDD
voltage exceeds turn-on voltage and enters normal
operation; this high voltage startup circuit is shut down
to avoid power loss from startup resistor.
Figure 36 shows the characteristic curve of VDD voltage
and operating current IDD. When VDD voltage is lower
than VDD-PWM-OFF, FAN6921ML stops all switching
operation and turns off some unnecessary internal
circuit to reduce operating current. By doing so, the
period from VDD-PWM-OFF to VDD-OFF can be extended and
the hiccup mode frequency can be decreased to reduce
the input power in case of output short circuit. Figure 37
shows the typical waveforms of VDD voltage and gate
signal at hiccup mode operation.
is detected, FAN6921ML outputs PWM gate signal to
turn on the switch and begin a new switching cycle.
With green mode and valley detection, at light load
condition; power system can perform extended valley
switching at DCM operation and further reduce
switching loss for better conversion efficiency. The FB
pin voltage versus tOFF-MIN time characteristic curve is
shown in Figure 38. As Figure 38 shows, FAN6921ML
can extend tOFF time up to 2.5ms, which is around
400Hz switching frequency.
Referring to Figure 1 and Figure 2, FB pin voltage is not
only used to receive secondary feedback signal to
determine gate on time, but also determines PFC stage
on or off status. At no-load or light-load conditions, if PFC
stage is set to be off; that can reduce power consumption
from PFC stage switching device and increase
conversion efficiency. When output loading is decreased,
the FB pin voltage becomes lower and, therefore, the
FAN6921ML can detect the output loading level
according to the FB pin voltage to control the on / off
status of the PFC part.
Figure 36. VDD vs. IDD-OP Characteristic Curve
Figure 37. Typical Waveform of VDD Voltage and
Gate Signal in Hiccup Mode Operation
Green-Mode Operation and PFC-ON / OFF Control
(FB Pin)
Green mode is used to further reduce power loss in the
system (e.g. switching loss). It uses an off-time
modulation technique to regulate switching frequency
according to FB pin voltage. When output loading is
decreased, FB voltage becomes lower due to secondary
feedback movement and the tOFF-MIN is extended. After
tOFF-MIN (determined by FB voltage), the internal valley
detection circuit is activated to detect the valley on the
drain voltage of the PWM switch. When the valley signal
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
Figure 38. VFB Voltage vs. tOFF-MIN Time
Characteristic Curve
Valley Detection (DET Pin)
When FAN6921ML operates in green mode, tOFF-MIN is
determined by the green mode circuit according to FB
pin voltage level. After tOFF-MIN, the internal valley-
detection circuit is activated. During the off time of the
PWM switch, when transformer inductor current
discharges to zero; the transformer inductor and
parasitic capacitor of PWM switch start to resonate
concurrently. When the drain voltage on the PWM
switch falls, the voltage across on auxiliary winding VAUX
also decreases since auxiliary winding is coupled to
primary winding. Once the VAUX voltage resonates and
falls to negative, VDET voltage is clamped by the DET pin
(refer to Figure 39) and FAN6921ML is forced to flow
out a current IDET. FAN6921ML reflects and compares
this IDET current. If this source current rises to a
threshold current, PWM gate signal is sent out after a
fixed delay time (200ns typical).
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