FAN6921ML Datasheet, PDF(20/23 Page) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

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FAN6921ML Datasheet, PDF (20/23 Pages) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

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Protection for PWM Stage

VDD Pin Over-Voltage Protection (OVP)

VDD over-voltage protection is used to prevent device

damage once VDD voltage is higher than device stress

rating voltage. In case of VDD OVP, the controller stops

all switching operation immediately and enters latch-off

mode until the AC plug is removed.

Adjustable Over-Temperature Protection and

Externally Latch Triggering (RT Pin)

Figure 43 is a typical application circuit with an internal

block of RT pin. As shown, a constant current IRT flows

out from the RT pin, so the voltage VRT on RT pin can

be obtained as IRT current multiplied by the resistor,

which consists of NTC resistor and RA resistor. If the RT

pin voltage is lower than 0.8V and lasts for a debounce

time, latch mode is activated and stops all PFC and

PWM switching.

The RT pin is usually used to achieve over-temperature

protection with a NTC resistor and provides external

latch triggering for additional protection. Engineers can

use an external triggering circuit (e.g. transistor) to pull

low the RT pin and activate controller latch mode.

Generally, the external latch triggering needs to activate

rapidly since it is usually used to protect power system

from abnormal conditions. Therefore, the protection

debounce time of the RT pin is set to around 100Âµs

once RT pin voltage is lower than 0.5V.

For over-temperature protection, because the

temperature would not change immediately; the RT pin

voltage is reduced slowly as well. The debounce time

for adjustable OTP should not need a fast reaction. To

prevent improper latch triggering on the RT pin due to

exacting test conditions (e.g. lightning test); when the

RT pin triggering voltage is higher than 0.5V, the

protection debounce time is set to around 10ms. To

avoid improper triggering on the RT pin, it is

recommended to add a small value capacitor (e.g.

1000pF) paralleled with NTC and RA resistor.

FA N 692 1

Adjustable Over-

Temperature protection &

External Latch triggering

I RT=10 0ÂµA

NTC

0.8V

RRT

0.5V

Deboun ce

time

Latched

11 0Âµs

10ms

Figure 43. Adjustable Over-Temperature Protection

Output Over-Voltage Protection (DET Pin)

Referring to Figure 44, during the discharge time of

PWM transformer inductor; the voltage across on

auxiliary winding is reflected from secondary winding

and therefore the flat voltage on the DET pin is

proportional to the output voltage. FAN6921ML can

sample this flat voltage level after a tOFF blanking time to

perform output over-voltage protection. This tOFF

blanking time is used to ignore the voltage ringing from

leakage inductance of PWM transformer. The sampled

flat voltage level is compared with internal threshold

voltage 2.5V and, once the protection is activated,

FAN6921ML enters latch mode.

The controller can protect rapidly by this kind of cycle-

by-cycle sampling method in the case of output over

voltage. The protection voltage level can be determined

by the ratio of external resistor divider RA and RDET. The

flat voltage on DET pin can be expressed by the

following equation:

( ) VDET =

ÃVO

RDET +

(2)

PWM

Gate

VAUX

PFC

V VO

DET

RDET +

sampling

here

tOFF

blanking

0.3V

Figure 44. Operation Waveform of Output

Over-Voltage Detection

FAN6921ML â¢ Rev. 1.0.1

www.fairchildsemi.com

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