FAN6921ML Datasheet, PDF (21/23 Pages) Fairchild Semiconductor – Integrated Critical Mode PFC/Quasi-Resonant Current Mode PWM Controller

Open-Loop, Short-Circuit, and Overload Protection
(FB Pin)
Referring to Figure 45, outside of FAN6921ML; the FB
pin is connected to the collector of transistor of an opto-
coupler. Inside of FAN6921ML, the FB pin is connected
to an internal voltage bias through a resistor of ~5kΩ.
As the output loading is increased, the output voltage is
decreased and the sink current of transistor of opto-
coupler on primary side is reduced. So the FB pin
voltage is increased by internal voltage bias. In the case
of an open loop, output short circuit, or overload
conditions; this sink current is further reduced and the
FB pin voltage is pulled to high level by internal bias
voltage. When the FB pin voltage is higher than 4.2V for
50ms, the FB pin protection is activated.
Under-Voltage Lockout (UVLO, VDD Pin)
Referring to Figure 36 and Figure 37, the turn-on and
turn-off VDD threshold voltages are fixed at 18V and
10V, respectively. During startup, the hold-up capacitor
(VDD capacitor) is charged by the HV startup current
until VDD voltage reaches the turn-on voltage. Before the
output voltage rises to rated voltage and delivers energy
to the VDD capacitor from auxiliary winding, this hold-up
capacitor has to sustain the VDD voltage energy for
operation. When VDD voltage reaches turn-on voltage,
FAN6921ML starts all switching operation if no
protection is triggered before VDD voltage drops to turn-
off voltage VDD-PWM-OFF.
Figure 45. FB Pin Open-Loop, Short Circuit,
and Overload Protections
© 2010 Fairchild Semiconductor Corporation
FAN6921ML • Rev. 1.0.1
21
www.fairchildsemi.com