FAN54300 Datasheet, PDF (32/43 Pages) Fairchild Semiconductor – USB-Compliant, Dual-Power Input, Single-Cell, Li-Ion Switching Charger with USB-OTG Boost Regulator

I²C Interface
The serial interface is compatible with Standard, Fast, Fast
Plus, and High-Speed Modes per the I²C-Bus® specifications.
The SCL line is an input and its SDA line is a bi-directional
open-drain output; it can only pull down the bus when active.
The SDA line only pulls LOW during data reads and when
signaling ACK. All data is shifted in MSB (bit 7) first.
Bus Timing
As shown in Figure 55, data is normally transferred when SCL
is LOW. Data is clocked in on the rising edge of SCL.
Typically, data transitions shortly at or after the falling edge of
SCL to allow ample time for the data to set up before the next
SCL rising edge.
Data change allowed
SDA
SCL
T_H
T_SU
Figure 55. Data Transfer Timing
Each bus transaction begins and ends with SDA and SCL
HIGH. A transaction begins with a START condition, which is
defined as SDA transitioning from 1 to 0 with SCL HIGH, as
shown in Figure 56.
SDA
T_HD;STA
Slave Address
MS Bit
SCL
Figure 56. Start Bit
A transaction ends with a STOP condition, which is defined as
SDA transitioning from 0 to 1 with SCL HIGH, as shown in
Figure 57.
SDA
Slave Releases
ACK(0) or
NACK(1)
Master Drives
t_HD;STO
SCL
Figure 57. Stop Bit
During a read from the FAN54300 (see Figure 60), the master
issues a “REPEATED START” after sending the register
address and before resending the slave address. The
REPEATED START is a 1-to-0 transition on SDA while SCL is
HIGH, as shown in Figure 58.
High-Speed (HS) Mode
The protocols for High-Speed (HS), Low-Speed (LS), and
Fast-Speed (FS) Modes are identical, except the bus speed
for HS Mode is 3.4 MHz. HS Mode is entered when the bus
master sends the HS master code 00001XXX after a START
condition. The master code is sent in Fast or Fast-Plus Mode
(less than 1 MHz clock). Slaves do not ACK this transmission.
The master then generates a REPEATED START condition
(see Figure 58) that causes all slaves on the bus to switch to
HS Mode. The master then sends I²C packets, as described
above, using the HS Mode clock rate and timing.
The bus remains in HS Mode until a stop bit (Figure 57) is
sent by the master. While in HS Mode, packets are separated
by REPEATED START conditions (Figure 58).
SDA
Slave Releases
ACK(0) or
NACK(1)
t_SU;STA
t_HD;STA
SLADDR
MS Bit
SCL
Figure 58. Repeated Start Timing
Read and Write Transactions
The following figures outline the sequences for data read and
write. Bus control is signified by the shading of the packet,
defined as ^{Master Drives Bus} and
All addresses and data are MSB first.
Slave Drives Bus _.
Table 10. Bit Definitions for Figure 59 and Figure 60
Symbol
Definition
S START, see Figure 56.
A
ACK. The slave drives SDA to 0 to acknowledge
the preceding packet.
A
NACK. The slave sends a 1 to NACK the
preceding packet.
R Repeated START, see Figure 58
P STOP, see Figure 57.
7 bits
0
8 bits
0
S Slave Address 0 A
Reg Addr
A
8 bits
Data
Figure 59. Write Transaction
7 bits
0
S Slave Address 0 A
8 bits
Reg Addr
0
7 bits
0
A R Slave Address 1 A
Figure 60. Read Transaction
0
AP
8 bits
Data
1
AP
© 2010 Fairchild Semiconductor Corporation
FAN54300 • Rev. 1.0.4
32
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