FAN54300 Datasheet, PDF (24/43 Pages) Fairchild Semiconductor – USB-Compliant, Dual-Power Input, Single-Cell, Li-Ion Switching Charger with USB-OTG Boost Regulator

V_OREG
I_OCHARGE
V_SHORT
I_SHORT
I_CHARGE
V ^BAT
I_TERM
PRE- CURRENT REGULATION
VOLTAGE
CHARGE
REGULATION
Figure 46. Charge Curve when PWRIN Limitations
Don’t Limit ICHARGE
V_OREG
V_SHORT
I_SHORT
V ^BAT
I_CHARGE
I_TERM
PRE- CURRENT REGULATION
VOLTAGE
CHARGE
REGULATION
Figure 47. Charge Curve when PWRIN Limits ICHARGE
PWRIN limitations are controlled either by:
 IBUSLIM: These bits set the maximum amount of current
that the charger draws from VBUS; OR
 SP_CHARGER: For power-limited chargers, the
FAN54300 limits current draw when the charging source
drops to the voltage programmed by the SP_CHARGER
bits. This allows “travel adapters” to be accommodated
without host software overhead. The SP_CHARGER
control loop applies to both VIN and VBUS.
Assuming VOREG is programmed to the cell’s fully charged
“float” voltage, the current the battery accepts with the PWM
regulator limiting its output (sensed at VBAT) to VOREG
declines and the charger enters the voltage regulation phase
of charging. When the current declines to the programmed
ITERM value, the charge cycle is complete. Charge current
termination can be disabled by resetting the TE bit.
Charger Programmability
Throughout this document, any parameter that ends in “U”
applies when charging from VBUS and any parameter ending in
“V” applies when charging from VIN. Parameters set with slave
address D6 are applied when charging from VBUS. Parameters
set with slave address D4 are applied when charging from VIN.
The following charging and input power control parameters
can be programmed by the host through I²C.
Table 4. Programmable Charging Parameters
Parameter
Charging
Source
Name
Register
Output Voltage
Regulation
Battery Charging
Current Limit
Input Current Limit
Charge
Termination Limit
Special Charger
Minimum Voltage
Either
VBUS
VIN
VBUS
Either
Either
OREG
ICHGU
ICHGV
IBUSLIM
ITERM
REG2[7:2]
REG4[6:4]
REG4[6:3]
REG1[7:6]
REG4[2:0]
VSP
REG5[2:0]
The charger output or “float” voltage can be programmed by
the OREG bits from 3.5 V to 4.44 V in 20 mV increments.
Table 5. OREG Bits ( REG2 [7:2] ) vs. Charger V_OUT
(V_OREG) Float Voltage
Decimal Hex VOREG Decimal Hex VOREG
0
00
3.50
32
20
4.14
1
01
3.52
33
21
4.16
2
02
3.54
34
22
4.18
3
03
3.56
35
23
4.20
4
04
3.58
36
24
4.22
5
05
3.60
37
25
4.24
6
06
3.62
38
26
4.26
7
07
3.64
39
27
4.28
8
08
3.66
40
28
4.30
9
09
3.68
41
29
4.32
10
0A 3.70
42
2A 4.34
11
0B 3.72
43
2B 4.36
12
0C 3.74
44
2C 4.38
13
0D 3.76
45
2D 4.40
14
0E 3.78
46
2E 4.42
15
0F 3.80
47
2F
4.44
16
10
3.82
48
30
4.44
17
11
3.84
49
31
4.44
18
12
3.86
50
32
4.44
19
13
3.88
51
33
4.44
20
14
3.90
52
34
4.44
21
15
3.92
53
35
4.44
22
16
3.94
54
36
4.44
23
17
3.96
55
37
4.44
24
18
3.98
56
38
4.44
25
19
4.00
57
39
4.44
26
1A 4.02
58
3A 4.44
27
1B 4.04
59
3B 4.44
28
1C 4.06
60
3C 4.44
29
1D 4.08
61
3D 4.44
30
1E 4.10
62
3E 4.44
31
1F 4.12
63
3F
4.44
Note:
6. All register default settings are noted by bold typeface.
© 2010 Fairchild Semiconductor Corporation
FAN54300 • Rev. 1.0.4
24
www.fairchildsemi.com