FAN54300 Datasheet, PDF (25/43 Pages) Fairchild Semiconductor – USB-Compliant, Dual-Power Input, Single-Cell, Li-Ion Switching Charger with USB-OTG Boost Regulator

Charge Initiation
A new charge cycle begins when one of the following occurs:
 The battery voltage falls below VOREG - VRCH
 A power source is connected (PWRIN POR) and battery
voltage is below the weak-battery threshold (VLOWV).
 CE# and HZ_MODE are both cleared, after having been
set, and a power source is connected.
Charge Current Limit
The default charge current is limited by the IOLEVEL bit
( REG5[5] ). When this bit is set (default), charge current is
limited to 325 mA (22.1 mV across RSENSE) and the ICHG
bits are ignored. Resetting IOLEVEL allows the ICHG bits
to control the battery charge current limit.
Any attempt to write a value higher than 10 (0AH) results in
a value of 10 (0AH) written to the ICHGV bits (see Table 24).
Charge Termination Current Limit
Current charge termination is enabled when TE ( REG1[3] )
= 1. The current level is control by the ITERM bits (
REG4[2:0].
PWM Controller in Charge Mode
The IC uses a current-mode PWM controller to regulate the
output voltage and battery charge currents. A cycle-by-cycle
current limit of nominally 2.3 A, sensed through Q1, is used
to terminate tON. The synchronous rectifier, Q2, also has a
current limit that turns off Q2 at 160mA to prevent current
flow from the battery.
When the charge current drops below ~20 mA; the IC runs in
Asynchronous Mode, which prevents reverse current from
pumping up the input source.
Safety Timer (see Figure 52)
At the beginning of the charging process, the IC starts the
15-minute timer (t15MIN). When this timer expires, charging is
terminated and the CE# bit is set. Writing to any register
through I²C stops the t15MIN timer, which, in turn, starts a
32-second timer (t32SEC). Setting the TMR_RST bit (REG0[1])
resets the t32SEC timer. If the t32SEC timer times out, all
registers (except SAFETY) are set to their default values, a
Timer Fault (110) is reported in the fault register, and
charging resumes using the default values with the t15MIN
timer running.
Since there is only one t32SEC timer on the IC, writing to either
TMR_RST bit in either CONTROL0_U or CONTROL0_V
resets the timer. The t32SEC timer starts with an I²C WRITE to
either slave address. Timer faults are reported in both U and
V registers. A t32SEC fault resets U and V registers 1 – 5.
Normally, charging is controlled by the host with the t32SEC
timer running to ensure that the host is active. Charging with
the t15MIN timer running is used for charging that is
unattended by the host, which would occur when VBAT is
insufficient to power the host processor. If the 15-minute
timer expires, the IC turns off the charger and indicates a
timer fault (110) on the FAULT bits ( REG0[2:0] ). This
prevents overcharge if the host fails to reset the t32SEC timer.
The CE# bit is set in the registers where the power sources
are connected. For example, if VIN and VBUS are both
connected when the t15MIN timer expires, CE#_V and CE_U
are both set.
Reset Bit
Setting the RESET bit ( Reg4[7] ) resets all registers for the
slave address used to set the RESET bit. When the RESET
bit is set, the t32SEC timer is reset and stopped, charging
stops and the IC goes to Charge Configuration Mode (see
Figure 50). If VBAT < VOREG, charging begins in 15-Minute
Mode 262 ms after the RESET bit is set.
PWRIN Validation, Notification, and
Non-Compliant Power Source Rejection
Whenever either VBUS_CON or VIN_CON bits have been
set, the STAT pin pulses to notify the host processor of a
change in status on the input power supply.
Before attempting to charge, the IC attempts to validate its
input source by loading the appropriate source with 110  to
ensure that the source stays between 4.4 V and VINOVP for
32 ms. If the input source fails validation, STAT enunciates a
fault and the fault bits are set according to the condition of
the input source (OVP or poor input source). The PWRIN
validation sequence always occurs before charging is
initiated or re-initiated (for example, after a PWRIN OVP
fault, a VRCH recharge initiation, or resetting the HZ bit). The
32 ms validation time ensures that unfiltered 50/60 Hz
chargers and other non-compliant chargers are rejected.
2.5 V Regulator Operation
When the VIN_CON bit is set, indicating that the VIN power
source has been plugged in, the V2V5 regulator is enabled.
USB-Friendly Boot Sequence
(see Figure 48)
At PWRIN POR, when the battery voltage is above the
weak-battery threshold (VLOW), the IC goes into Charge
Configuration Mode unless the t32SEC timer is enabled by an
I²C write. In that case, the IC begins to charge with the
existing register settings.
If VBAT < VLOW, the IC goes into Charge Configuration Mode
if the t32SEC timer is not enabled. If VBAT < VOREG, the
registers reset and charging begins in 15-Minute Mode.
During 15-Minute Mode, the charger uses an input current
limit controlled by the OTG pin when charging from VBUS
(100mA if OTG is LOW and 500mA if OTG is HIGH).
Even if charging from VIN, the charging current is limited to
325 mA (22.14 mV across 68m) after the registers are
reset. This feature can revive a cell whose voltage is too low
for reliable host operation until the battery has sufficient
charge for the host to boot up and set charge parameters.
Charging continues in the absence of host communication
even after the battery has reached VOREG, with a default
value of 3.54 V, and the charger remains active until t15MIN
times out.
Once the host processor begins writing to the IC, charging
parameters are set by the host, which must continually reset
the t32SEC timer to continue charging using programmed
charging parameters. If t32SEC.times out, the register defaults
are loaded, the FAULT bits are set to 110, STAT is pulsed,
and charging continues with default charge parameters.
At PWRIN POR, if VBAT < VLOW and HZ or CE# were set
previously, the IC goes into HZ state, which causes the
registers to reset, clearing the HZ and CE# bits when t32SEC
expires and beginning t15MIN charging unless the host
processor sets the TMR_RST bit.
© 2010 Fairchild Semiconductor Corporation
FAN54300 • Rev. 1.0.4
25
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