XRT75R12D_06 Datasheet, PDF (90/134 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET

XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
TABLE 40: ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC
BIT 7
Msb
R/W
BIT 6
R/W
BIT 5
R/W
BIT 4
R/W
BIT 3
R/W
BIT 2
R/W
BIT 1
R/W
BIT 0
Ls bit
R/W
Each channel contains a dedicated 16 bit PRBS error counter. When enabled this counter will accumulate
PRBS errors (as well as excess zeros and LCVs). The LS byte will "carry" a one over to the MS byte each time
it rolls over from 255 to zero until the MS byte also reaches 255. When both counters reach 255, no further
errors will be accumulated and "all ones" will signify an overflow condition.
The counter can be read while in the active count mode. Either register may be read "on the fly" and the other
byte will be simultaneously transferred into the channel’s Error Holding register. The holding register may then
be read to supply the Host with a correct 16 bit count (as of the instant of reading). With this mechanism, the
Host could rapidly cycle thru reading all twelve counters in order (storing the read byte in scratch RAM) and
then come back and read the second byte from each holding register to form the 16 bit accumulation in the
Host system.
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