XRT75R12D_06 Datasheet, PDF (16/134 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET

XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
MICROPROCESSOR PARALLEL INTERFACE -
PIN #
K25
M22
M23
M24
K26
L26
M26
N26
P22
R26
T26
U26
R25
R24
R23
R22
SIGNAL NAME
Addr0
Addr1
Addr2
Addr3
Addr4
Addr5
Addr6
Addr7
D0
D1
D2
D3
D4
D5
D6
D7
TYPE
I
DESCRIPTION
An eight bit direct address bus that specifies the source/destination register for a
Read or Write operation.
I/O ^{An eight bit bi-directional data bus that provides the data into the LIU for a Write}
operation or the data out to the Host for a Read operation.
P26
INT
O Interrupt Active Output (active low)
Normally, this output pin will be pulled "High". However, if the user enables
interrupts within the LIU, and if those conditions occur, the XRT75R12D will sig-
nal an interrupt from the Microprocessor by pulling this output pin "Low". The
Host Microprocessor must ascertain the source of the interrupt and service it.
Reading the source of the interupt will clear the flag and the INT pin will go back
high unless another interrupt has gone active.
NOTES:
1. This pin will remain "Low" until the Interrupt has been serviced.
2. This pin must be pulled "High" with a 3kΩ ± 1% resistor.
N2
RESET
I RESET Input
Pulsing this input "Low" causes the XRT75R12D to reset the contents of the on-
chip Command Registers to their default values. As a consequence, the
XRT75R12D will then also be operating in its default condition.
For normal operation this input pin should be at a logic "High".
NOTE: This input pin is internally pulled high.
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