XRT75R12D_06 Datasheet, PDF (86/134 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET

XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6
BIT NUMBER
NAME
TYPE
DESCRIPTION
1
STS-1/DS3_n
R/W STS-1/DS3 Mode Select - Channel_n:
This READ/WRITE bit-field, along with Bit 2 (E3_n) is used to configure a
given channel into either the DS3, E3 or STS-1 Modes.
This bit-field is ignored if Bit 2 (E3_n) has been set to "1".
If Bit 2 (E3_n) is a 0:
0 - Configures Channel_n to operate in the DS3 Mode.
1 - Configures Channel_n to operate in the STS-1 Mode .
0
SR/DR_n
R/W Single-Rail/Dual-Rail Select - Channel_n:
This READ/WRITE bit-field is used to configure Channel_n to operate in
either the Single-Rail or Dual-Rail Mode.
If the user configures the Channel to operate in the Single-Rail Mode, the
following will happen.
• The B3ZS/HDB3 Encoder and Decoder blocks (within Channel_n) will be
enabled.
• The Transmit Section of Channel_n will accept all of the outbound data
(from the System-side Equipment) via the TxPOS_n input pin.
• The Receive Section of each channel will output all of the recovered data
(to the System-side Equipment) via the RxPOS_n output pin.
• The corresponding RNEG/LCV_n output pin will now function as the LCV
(Line Code Violation or Excessive Zero Event) indicator output pin for
Channel_n.
If the user configures Channel_n to operate in the Dual-Rail Mode, the fol-
lowing will happen.
• The B3ZS/HDB3 Encoder and Decoder blocks of Channel_n will be
disabled.
• The Transmit Section of Channel_n will be configured to accept positive-
polarity data via the TxPOS_n input pin and negative-polarity data via the
TxNEG_n input pin.
• The Receive Section of Channel_n will pulse the RxPOS_n output pin
"High" (for one period of RCLK_n) for each time a positive-polarity pulse is
received via the RTIP_n/RRING_n input pins. Likewise, the Receive
Section of each channel will pulse the RxNEG_n output pin "High" (for
one period of RxCLK_n) for each time a negative-polarity pulse is
received via the RTIP_n/RRING_n input pins.
0 - Configures Channel_n to operate in the Dual-Rail Mode.
1 - Configures Channel_n to operate in the Single-Rail Mode.
TABLE 34: XRT75R12D REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_N)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved
JA RESET
Ch_n
JA1 Ch_n JA in Tx Path JA0 Ch_n
Ch_n
R/W
R/W
R/W
R/W
81