XRT75R12D_06 Datasheet, PDF (111/134 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET

XRT75R12D
REV. 1.0.1 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
8.3.4 Why are we talking about Pointer Adjustments?
The overall SONET network consists of numerous "Synchronization Islands". As a consequence, whenever a
SONET signal is being transmitted from one "Synchronization Island" to another; that SONET signal will
undergo a "clock domain" change as it traverses the network. This clock domain change will result in periodic
pointer-adjustments occurring within this SONET signal. Depending upon the direction of this "clock-domain"
shift that the SONET signal experiences, there will either be periodic "incrementing" pointer-adjustment events
or periodic "decrementing" pointer-adjustment events within this SONET signal.
Regardless of whether a given SONET signal is experiencing incrementing or decrementing pointer
adjustment events, each pointer adjustment event will result in an abrupt 8-bit shift in the position of the SPE
within the STS-1 data-stream. If this STS-1 signal is transporting an "asynchronously-mapped" DS3 signal;
then this 8-bit shift in the location of the SPE (within the STS-1 signal) will result in approximately 8UIpp of jitter
within the asynchronously-mapped DS3 signal, as it is de-mapped from SONET. In “Section 8.5, A Review of
the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications” on
page 107 we will discuss the "Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-
253-CORE. However, for now we will simply state that this 8UIpp of intrinsic jitter far exceeds these "intrinsic
jitter" requirements.
In summary, pointer-adjustments events are a "fact of life" within the SONET/SDH network. Further, pointer-
adjustment events, within a SONET signal that is transporting an asynchronously-mapped DS3 signal, will
impose a significant impact on the Intrinsic Jitter and Wander within that DS3 signal as it is de-mapped from
SONET.
8.4 Clock Gapping Jitter
In most applications (in which the LIU will be used in a SONET De-Sync Application) the user will typically
interface the LIU to a Mapper Device in the manner as presented below in Figure 54.
FIGURE 54. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION
STS-N Signal
De-Mapped (Gapped)
DS3 Data and Clock
DDSS33ttooSSTTSS-N-N
MMaappppeerr//
DDeemmaappppeerr
IICC
TPDATA_n input pin
LLIIUU
TCLK_n input
In this application, the Mapper IC will have the responsibility of receiving an STS-N signal (from the SONET
Network) and performing all of the following operations on this STS-N signal.
• Byte-de-interleaving this incoming STS-N signal into N STS-1 signals
• Terminating each of these STS-1 signals
• Extracting (or de-mapping) the DS3 signal(s) from the SPEs within each of these terminated STS-1 signals.
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