XRT75R12D_06 Datasheet, PDF (24/134 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET

XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1
2.0 CLOCK SYNTHESIZER
The LIU uses a flexible user interface for accepting clock references to generate the internal master clocks
used to drive the LIU. The reference clock used to supply the microprocessor timing is generated from the DS-
3 or SFM clock input. Therefore, if the chip is configured for STS-1 only or E3 only, then the DS-3 input pin
must be connected to the STS-1 pin or E3 pin respectively. In DS-3 mode or when SFM is used, the STS-1
and E3 input pins can be left unconnected. If SFM is enabled by pulling the SFM_EN pin "High", 12.288MHz is
the only clock reference necessary to generate DS-3, E3, or STS-1 line rates and the microprocessor timing.
A simplified block diagram of the clock synthesizer is shown in Figure 3. Reference clock performance
specifications can be found on Table 2 below.
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR
SFM_EN STS-1Clk/12M DS3Clk
E3Clk
Clock Synthesizer
0
µProcessor
1
CLKOUT_n
LOL_n
TABLE 2: REFERENCE CLOCK PERFORMANCE SPECIFICATIONS
SYMBOL
PARAMETER
MIN
TYP
REF_DUTY Reference Clock Duty Cycle
40
REF_{E3 E3 Reference Clock Frequency Tolerance}¹
-20
REF_{DS3 DS3 Reference Clock Frequency Tolerance}¹
-20
REF_{STS1 STS-1 Reference Clock Frequency Tolerance}¹
-20
REF_{SFM SFM Reference Clock Frequency Tolerance}¹
-20
t_{RISE_REFCLK} Reference Clock Rise Time (10% to 90%)
t_{FALL_REFCLK} Reference Clock Fall Time (90% to 10%)
CLK_{JIT Reference Clock Jitter Stability}²
MAX
60
+20
+20
+20
+20
5
5
0.005
UNITS
%
ppm
ppm
ppm
ppm
ns
ns
UI_p2p
NOTES:
1. Required to meet Bellcore GR-499 specification on frequency stability requirements. However, the LIU can
functionally operate with ±100 ppm without meeting the required specifications.
2. Reference clock jitter limits are required for the transmit output to meet ITU-T and Bellcore system level jitter
requirements.
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