XRT75R12D_06 Datasheet, PDF (87/134 Pages) Exar Corporation – TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET

XRT75R12D
REV. 1.0.1 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM7
BIT NUMBER
NAME
TYPE
DESCRIPTION
7-4
Reserved
3
JA RESET Ch_n R/W Jitter Attenuator RESET - Channel_n:
Writing a "0 to 1" transition within this bit-field will configure the Jitter Attenu-
ator (within Channel_n) to execute a RESET operation.
Whenever the user executes a RESET operation, then following will occur.
• The READ and WRITE pointers (within the Jitter Attenuator FIFO) will be
reset to their default values.
• The contents of the Jitter Attenuator FIFO will be flushed.
NOTE: The user must follow up any "0 to 1" transition with the appropriate
write operate to set this bit-field back to "0", in order to resume
normal operation with the Jitter Attenuator.
2
JA1 Ch_n
R/W Jitter Attenuator Configuration Select Input - Bit 1:
This READ/WRITE bit-field, along with Bit 0 (JA0 Ch_n) is used to do any of
the following.
• To enable or disable the Jitter Attenuator corresponding to Channel_n.
• To select the FIFO Depth for the Jitter Attenuator within Channel_n.
The relationship between the settings of these two bit-fields and the Enable/
Disable States, and FIFO Depths is presented below.
JA0 JA1
0
0
0
1
1
0
1
1
Jitter Attenuator Mode
FIFO Depth = 16 bits
FIFO Depth = 32 bits
Disabled
Disabled
1
JA in Tx Path Ch_n R/W Jitter Attenuator in Transmit/Receive Path Select Bit:
This input pin is used to configure the Jitter Attenuator (within Channel_n) to
operate in either the Transmit or Receive path, as described below.
0 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Receive Path.
1 - Configures the Jitter Attenuator (within Channel_n) to operate in the
Transmit Path.
0
JA0 Ch_n
R/W Jitter Attenuator Configuration Select Input - Bit 0:
See the description for Bit 2 (JA1 Ch_n).
TABLE 35: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER MSBYTE REGISTERS (EM_N)
ADDRESS
LOCATION
0
1
2
3
4
5
6
7 89 A
B
C DE F
0x0- ^APST IER0 ISR0 AS0 TC0 RC0 CC0 JA0 ^APSR
EM0 EL0 EH0
0X1-
IER1 ISR1 AS1 TC1 RC1 CC1 JA1
EM1 EL1 EH1
0x2-
IER2 ISR2 AS2 TC2 RC2 CC2 JA2
EM2 EL2 EH2
82