XRT16C854 Datasheet, PDF (9/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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REV. 3.0.1
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR16C854 (854) integrates the functions of 4 enhanced 16C550 Universal Asynchronous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 128-bytes of transmit and receive FIFOs, automatic RTS/CTS hardware
flow control with hysteresis control, automatic Xon/Xoff and special character software flow control,
programmable transmit and receive FIFO trigger levels, FIFO level counters, infrared encoder and decoder
(IrDA ver 1.0), programmable baud rate generator with a prescaler of divide by 1 or 4, and data rate up to 2
Mbps. The XR16C854 can operate at 3.3 or 5 volts. The 854 is fabricated with an advanced CMOS process.
Enhanced FIFO
The 854 QUART provides a solution that supports 128 bytes of transmit and receive FIFO memory, instead of
64 bytes provided in the ST16C654 and 16 bytes in the ST16C554, or one byte in the ST16C454. The 854 is
designed to work with high performance data communication systems, that require fast data processing time.
Increased performance is realized in the 854 by the larger transmit and receive FIFOs, FIFO trigger level
control, FIFO level counters and automatic flow control mechanism. This allows the external processor to
handle more networking tasks within a given time. For example, the ST16C554 with a 16 byte FIFO, unloads
16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including start/stop bits at
115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. However
with the 128 byte FIFO in the 854, the data buffer will not require unloading/loading for 12.2 ms. This increases
the service interval giving the external CPU additional time for other applications and reducing the overall
UART interrupt servicing time. In addition, the programmable FIFO level trigger interrupt and automatic
hardware/software flow control is uniquely provided for maximum data throughput performance especially
when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s bandwidth
requirement, increases performance, and reduces power consumption.
Data Rate
The 854 is capable of operation up to 2 Mbps at 5V with 16x internal sampling clock rate. The device can
operate with a crystal oscillator of up to 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of
32 MHz on XTAL1 pin. With a typical crystal of 14.74128 MHz and through a software option, the user can set
the prescaler bit for data rates of up to 921.6 kbps.
Enhanced Features
The rich feature set of the 854 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder
interface, modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility
for turning off software flow control with any incoming (RX) character. In the 16 mode INTSEL and MCR bit-3
can be configured to provide a software controlled or continuous interrupt capability. Due to pin limitations for
the 64 pin package of the 854, this feature is offered in two different LQFP packages. The XR16C854DCV
operates in the continuous interrupt enable mode by internally bonding INTSEL to VCC. The XR16C854CV
operates in conjunction with MCR bit-3 by internally bonding INTSEL to GND.
The 68 and 100 pin XR16C854 packages offer a clock prescaler select pin to allow system/board designers to
preset the default baud rate table on power up. The CLKSEL pin selects the div-by-1 or div-by-4 prescaler for
the baud rate generator. It can then be overridden following initializatioin by MCR bit-7.
The 100 pin package offer several other enhanced features. These features include a CHCCLK clock input,
FSTAT register and separate IrDA TX outputs. The CHCCLK must be connected to the XTAL2 pin for normal
operation or to external MIDI (Music Instrument Digital Interface) oscillator for MIDI applications. A separate
register (FSTAT) is provided for monitoring the real time status of the FIFO signals TXRDY# and RXRDY# for
each of the four UART channels (A-D). This reduces polling time involved in accessing individual channels.
The 100 pin QFP package also offers four separate IrDA (Infrared Data Association Standard) TX outputs for
Infrared applications. These outputs are provided in addition to the standard asynchronous modem data
outputs.
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