XRT16C854 Datasheet, PDF (6/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
Pin Description
NAME
64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION
TXRDY#
-
39
45
O Transmitter Ready (active low). This output is a logically wire-
ORed status of TXRDY# A-D. See Table 5. If this output is
unused, leave it unconnected.
RXRDY#
-
38
44
O Receiver Ready (active low). This output is a logically wire-ORed
status of RXRDY# A-D. See Table 5. If this output is unused,
leave it unconnected.
FSRS#
-
-
76
I FIFO Status Register Select (active low input with internal pull-up).
The content of the FSTAT register is placed on the data bus when
this pin becomes active. However it should be noted, D0-D3 con-
tain the inverted logic states of TXRDY# A-D pins, and D4-D7 the
logic states (un-inverted) of RXRDY# A-D pins. Address line is not
required when reading this status register.
MODEM OR SERIAL I/O INTERFACE
TXA
8
17
14
O UART channels A-D Transmit Data and infrared transmit data.
TXB
10
19
16
TXC
39
51
65
TXD
41
53
67
Standard transmit and receive interface is enabled when MCR[6] =
0. In this mode, the TX signal will be a logic 1 during reset, or idle
(no data). Infrared IrDA transmit and receive interface is enabled
when MCR[6] = 1. In the Infrared mode, the inactive state (no
data) for the Infrared encoder/decoder interface is a logic 0.
IRTXA
-
IRTXB
-
IRTXC
-
IRTXD
-
-
6
O UART channel A-D Infrared Transmit Data. The inactive state (no
-
24
-
57
-
75
data) for the Infrared encoder/decoder interface is a logic 0.
Regardless of the logic state of MCR bit-6, this pin will be operating
in the Infrared mode.
RXA
62
7
97
I UART channel A-D Receive Data or infrared receive data. Normal
RXB
20
29
34
RXC
29
41
47
RXD
51
63
85
receive data input must idle at logic 1 condition. The infrared
receiver pulses typically idles at logic 0 but can be inverted by soft-
ware control prior going in to the decoder, see FCTR[2].
RTSA#
5
14
11
O UART channels A-D Request-to-Send (active low) or general pur-
RTSB#
13
22
19
pose output. This output must be asserted prior to using auto RTS
RTSC#
36
48
62
RTSD#
44
56
70
flow control, see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and
IER[6]. Also see Figure 11. If these outputs are not used, leave
them unconnected.
CTSA#
2
11
8
I UART channels A-D Clear-to-Send (active low) or general purpose
CTSB#
16
25
22
input. It can be used for auto CTS flow control, see EFR[7], and
CTSC#
33
45
59
CTSD#
47
59
73
IER[7]. Also see Figure 11. These inputs should be connected
to VCC when not used.
DTRA#
3
12
9
O UART channels A-D Data-Terminal-Ready (active low) or general
DTRB#
15
24
21
DTRC#
34
46
60
purpose output. If these outputs are not used, leave them uncon-
nected.
DTRD#
46
58
72
DSRA#
1
10
7
I UART channels A-D Data-Set-Ready (active low) or general pur-
DSRB#
17
26
23
pose input. This input should be connected to VCC when not used.
DSRC#
32
44
58
DSRD#
48
60
74
6