XRT16C854 Datasheet, PDF (54/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION ................................................................ 26
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 27
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 27
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 27
TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL ..................................................................................................................... 28
4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 28
TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ............................................................................................ 29
4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 30
TABLE 12: PARITY SELECTION ........................................................................................................................................................ 31
4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 32
TABLE 13: INT OUTPUT MODES ..................................................................................................................................................... 32
4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 33
4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 34
4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 35
4.11 ENHANCED MODE SELECT REGISTER (EMSR) ...................................................................................... 35
TABLE 14: SCRATCHPAD SWAP SELECTION .................................................................................................................................... 35
TABLE 15: AUTO RTS HYSTERESIS ............................................................................................................................................... 36
4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY .......................................................................................... 36
4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 36
4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 36
4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 36
4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY ..................................................................................................... 36
4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY .................................................................................. 37
4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE ........................................................................ 37
TABLE 16: TRIGGER TABLE SELECT................................................................................................................................................ 37
4.19 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ........................................................................ 37
TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS ........................................................................................................................ 38
4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 39
4.21 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ................................................................................... 39
TABLE 18: UART RESET CONDITIONS FOR CHANNELS A-D.................................................................................................. 40
ABSOLUTE MAXIMUM RATINGS......................................................................................................................41
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: = 15%) ..............................................41
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................41
TA=0o to 70oC (-40o to +85oC for industrial grade package), Vcc is 2.97 to 5.5V.................................................. 41
ELECTRICAL CHARACTERISTICS ................................................................................41
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................42
TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 2.97 TO 5.5V.........................42
FIGURE 14. CLOCK TIMING............................................................................................................................................................. 43
FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D .................................................................................................... 43
FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D .................................................................................. 44
FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D.................................................................................... 44
FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................... 45
FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................... 45
FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D ............................................................ 46
FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D .......................................................... 46
FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D........................................... 47
FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D............................................ 47
FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D............................... 48
PACKAGE DIMENSIONS .................................................................................................................................49
REVISION HISTORY.......................................................................................................................................52
TABLE OF CONTENTS ............................................................................................................ I
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