XRT16C854 Datasheet, PDF (10/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
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REV. 3.0.1
2.0 FUNCTIONAL DESCRIPTIONS
2.1 CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 854 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS# A-D, IOR# and IOW# or CS#, R/W#, A4 and A3 inputs.
All four UART channels share the same data bus for host operations. A typical data bus interconnection for
Intel and Motorola mode is shown in Figure 4.
FIGURE 4. XR16C854/854D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
UART_CSA#
UART_CSB#
UART_CSC#
UART_CSD#
UART_INTA
UART_INTB
UART_INTC
UART_INTD
UART_RESET
VCC
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
RESET
16/68#
VCC
TXA
RXA
DTRA#
UART ^RTSA#
Channel A CTSA#
DSRA#
CDA#
RIA#
UART
Channel B _Similar
to Ch A
UART
Channel C Similar
to Ch A
UART
Channel D Similar
to Ch A
GND
Intel Data Bus (16 Mode) Interconnections
VCC
Serial Interface of
RS-232
Serial Interface of
RS-232
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
R/W#
UART_CS#
UART_IRQ#
UART_RESET#
VCC
VCC
(no connect)
(no connect)
(no connect)
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
CSB#
CSC#
CSD#
IOR#
IOW#
CSA#
INTA
INTB
INTC
INTD
RESET#
16/68#
VCC
TXA
RXA
DTRA#
UART ^RTSA#
Channel A CTSA#
DSRA#
CDA#
RIA#
UART
Channel B _Similar
to Ch A
UART
Channel C Similar
to Ch A
UART
Channel D ^Similar
to Ch A
GND
Motorola Data Bus (68 Mode) Interconnections
VCC
Serial Interface of
RS-232
Serial Interface of
RS-232
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