XRT16C854 Datasheet, PDF (12/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
xr
REV. 3.0.1
2.6 Channels A-D Internal Registers
Each UART channel in the 854 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status
and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user
accessible scratchpad register (SPR).
Beyond the general 16C550 features and capabilities, the 854 offers enhanced feature registers (EMSR, FLVL,
EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow control,
Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO trigger
level control, and FIFO level counters. All the register functions are discussed in full detail later in “Section
3.0, UART INTERNAL REGISTERS” on page 23.
2.7 INT Ouputs for Channels A-D
The interrupt outputs change according to the operating mode and enhanced features setup. Table 3 and 4
summarize the operating behavior for the transmitter and receiver. Also see Figure 20 through 24.
TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D
FCTR
Bit-3
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin
INT Pin
0 0 = a byte in THR
1 = THR empty
1 0 = a byte in THR
1 = transmitter empty
FCR Bit-3 = 0
(DMA Mode Disabled)
FCR Bit-3 = 1
(DMA Mode Enabled)
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty
0 = FIFO above trigger level
1 = FIFO below trigger level or
transmitter empty
0 = FIFO above trigger level
1 = FIFO below trigger level or FIFO
empty
0 = FIFO above trigger level
1 = FIFO below trigger level or
transmitter empty
TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D
FCR BIT-0 = 0
(FIFO DISABLED)
FCR BIT-0 = 1 (FIFO ENABLED)
INT Pin 0 = no data
1 = 1 byte
FCR Bit-3 = 0
(DMA Mode Disabled)
0 = FIFO below trigger level
1 = FIFO above trigger level
FCR Bit-3 = 1
(DMA Mode Enabled)
0 = FIFO below trigger level
1 = FIFO above trigger level
2.8 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A-D and TXRDY# A-D output pins. The transmit and receive FIFO trigger levels provide
additional flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the
transmitter is empty or has an empty location(s) for more data. The user can optionally operate the transmit
and receive FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the
DMA mode is disabled (FCR bit-3 = 0), the 854 is placed in single-character mode for data transmit or receive
operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the programmed trigger level. The following
table show their behavior. Also see Figure 20 through 24.
12