XRT16C854 Datasheet, PDF (37/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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REV. 3.0.1
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
4.17 FIFO Data Count Register (FC) - Read-Only
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Count
Register which is located in the general register set when FCTR bit-6 = 1 (Scratchpad Register Swap). It is
suggested to read the FIFO Level Count Register at the Scratchpad Register location when FCTR bit-6 = 1.
See Table 14.
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7] =
0) can be read via this register.
4.18 Feature Control Register (FCTR) - Read/Write
This register controls the XR16C854 new functions that are not available in ST16C554 or ST16C654.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See Table 15 for more details.
FCTR[2]: IrDA RX Inversion
• Logic 0 = Select RX input as encoded IrDA data (Idle state will be logic 0).
• Logic 1 = Select RX input as inverted encoded IrDA data (Idle state will be logic 1).
FCTR[3]: Auto RS-485 Direction Control
The Auto RS-485 Direction Control is not available in the XR16C854. See XR16C864. However, this bit
changes the TX Ready Interrupt behavior. See Table 3.
FCTR[5:4]: Transmit/Receive Trigger Table Select
See Table 11 for more details.
TABLE 16: TRIGGER TABLE SELECT
FCTR
BIT-5
FCTR
BIT-4
TABLE
0
0 Table-A (TX/RX)
0
1 Table-B (TX/RX)
1
0 Table-C (TX/RX)
1
1 Table-D (TX/RX)
FCTR[6]: Scratchpad Swap
• Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
• Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive holding register can be read via scratch pad register when this bit is set.
Enhanced Mode Select Register is selected when it is written into.
FCTR[7]: Programmable Trigger Register Select
• Logic 0 = Registers TRG and FC selected for RX.
• Logic 1 = Registers TRG and FC selected for TX.
4.19 Enhanced Feature Register (EFR) - Read/Write
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see Table 17). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
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