XRT16C854 Datasheet, PDF (36/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
EMSR[5:4]: Extended RTS Hysteresis
TABLE 15: AUTO RTS HYSTERESIS
xr
REV. 3.0.1
EMSR EMSR
BIT-5 BIT-4
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
FCTR
BIT-1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FCTR
BIT-0
RTS#
HYSTERESIS
(CHARACTERS)
0
0
1
±4
0
±6
1
±8
0
±8
1
±16
0
±24
1
±32
0
±40
1
±44
0
±48
1
±52
0
±12
1
±20
0
±28
1
±36
EMSR[7:6]: Reserved
4.12 FIFO Level Register (FLVL) - Read-Only
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this
is not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 14 for details.
4.13 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
• Baud Rate = (Clock Frequency / 16) / Divisor
See MCR bit-7 and the baud rate table also.
4.14 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x14 for XR16C854). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.15 Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.16 Trigger Level (TRG) - Write-Only
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
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