XRT16C854 Datasheet, PDF (15/54 Pages) Exar Corporation – 2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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REV. 3.0.1
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE
Data
Byte
T ran s m it
Holding
Register
(THR)
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X
Clock
Transmit Shift Register (TSR)
M
L
S
S
B
B
TXNOFIFO1
2.11.3 Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the TX FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when
the FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/TX FIFO becomes empty.
FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE
Data Byte
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
(Xoff1/2 and Xon1/2 Reg.
Auto Software Flow Control
RX FIFO
THR
THR Interrupt (ISR bit-1) falls
below the programmed Trigger
Level and then when becomes
empty. FIFO is Enabled by FCR
bit-0=1
16X Clock
Transmit Data Shift Register
(TSR)
T XF IF O 1
2.12 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 128 bytes of FIFO which includes a
byte-wide Receive Holding Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates
every bit on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit,
an internal receiver counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at
the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating
the start bit in this manner prevents the receiver from assembling a false character. The rest of the data bits
and stop bits are sampled and validated in this same manner to prevent false framing. If there were any
error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the
receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character or delay until
it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready
time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is
equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0.
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