XR28V382IL32-0A Datasheet, PDF (9/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
REV. 1.0.1
3.3V DUAL LPC UART WITH 128-BYTE FIFO
1.2.1.3 Stop Frame
After all IRQ/Data Frames have been completed, the host controller will terminate SERIRQ by a Stop frame.
Only the host controller can initiate the Stop frame by driving SERIRQ low for 2 or 3 clocks. If the Stop Frame is
low for 2 clocks, the next SERIRQ cycle will be the Quiet mode whereas if it is low for 3 clocks, the next
SERIRQ cycle will be the Continuous mode.
1.3 Watchdog Timer (WDT)
The WDT is typically used in a system to initiate any of the several types of corrective action, including
processor reset, power cycling, fail-safe activation etc. The Watchdog timer of V382 is an 8 bit counter
controlled by six registers. See ’Section 2.1.2.2, Watchdog Timer Registers (LDN = 0x08)’ WDTOUT#/
PS_WDT idles HIGH and will transition LOW when a time out occurs. The V382 provides three time intervals:
10 ms, 1s and 1 minute allowing for timeouts ranging from approximately 2.5 seconds to more than 4 hours.
See’Section2.1.2.2.4,WDTTimerStatusandControlRegister-Read/Write’tosetuptimeinterval.
1.4 UART
1.4.1 External Clock Input (CLKIN)
Along with LCLK, the V382 also needs an external clock for UART data communication. It can support any
clock up to 48MHz. The 24MHz and 48MHz are the standard clock frequencies supported by the V382. See
’Section 2.1.1.5, Clock Select Register - Read/Write’.
1.4.1.1 Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by Bit[1:0] of
Enhanced Multifunction Register - Read/Write.
Table 5 shows the standard data rates available with a 24 MHz external clock at 16X sampling rate and internal
clock frequency set to 1.8462 MHz. The divisor value can be calculated for DLL/DLM with the following
equation.
divisor (decimal) = (Internal clock frequency ) / (serial data rate x 16)
Table 8 lists the different internal clock settings.
TABLE 5: TYPICAL DATA RATES WITH A 1.8462MHZ INTERNAL CLOCK
BAUD Rate
(BPS)
DIVISOR FOR 16x DIVISOR FOR 16x
Clock (Decimal) Clock (HEX)
DLM
PROGRAM
VALUE (HEX)
DLL
PROGRAM
VALUE (HEX)
ACTUAL
BAUD RATE
DATA RATE
ERROR (%)
300
384
180
01
80
300.48
0.2
600
192
C0
00
C0
600.96
0.2
1200
96
60
00
60
1201.92
0.2
2400
48
30
00
30
2403.85
0.2
4800
24
18
00
18
4807.69
0.2
9600
12
0C
00
0C
9615.39
0.2
19200
6
06
00
06
19230.77
0.2
38400
3
03
00
03
38461.54
0.2
57600
2
02
00
02
57692.31
0.2
115200
1
01
00
01
115384.6
0.2
9