XR28V382IL32-0A Datasheet, PDF (24/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
3.3V DUAL LPC UART WITH 128-BYTE FIFO
REV. 1.0.1
Bits [4:3]: IR mode Enable
x ’00’ or ’01’ = Disable the IR function (default value is ’00’).
x ’10’ = Enable the IR function, active pulse is 1.6 us.
x ’11’ = Enable the IR function, active pulse is 3/16 bit time.
Bits [7:5]: Reserved
2.1.2.1.6
9-bit Mode Slave Address Register - Read/Write
This register indicates the slave address in 9-bit mode. This register along with the 9-bit mode slave address
mask register will determine the given address and broadcast address in 9-bit mode. The V382 will respond to
both the given address and the broadcast address.
2.1.2.1.7
9-bit Mode Slave Address Mask Register - Read/Write
This register indicates the slave address mask in 9-bit mode. This register along with the 9-bit mode slave
address register will determine the given address and broadcast address in 9-bit mode. The V382 will respond
to both the given address and the broadcast address.
x Given address: If bit n of the 9-bit mode slave address mask register is ’0’, then the corresponding bit of
given address is ’do not care’.
x Broadcast address: If bit n of the ORed 9-bit mode slave address register and 9-bit mode slave address
mask register is ’0’, then this bit n is a ’do not care’ bit. The remaining bit which is ’1’ is compared to the
received address.
TABLE 9: EXAMPLE
REGISTER
9-bit mode slave address register (0xF4)
9-bit mode slave address mask register (0xF5)
Given address
Broadcast address
EXAMPLE 1
11110100
01010101
x1x1x1x0
1111x1x1
EXAMPLE 2
00001111
10101010
0x0x1x1x
1x1x1111
EXAMPLE 3
01010101
11111111
01010101
11111111
EXAMPLE 4
11100111
00001111
xxxx0111
111x1111
2.1.2.1.8
FIFO Mode Select Register - Read/Write
This register selects FIFO depth and receiver trigger levels.
Bits [1:0]: FIFO size for TX/RX
x ’00’ = FIFO size is 16 bytes.
x ’01’ = FIFO size is 32 bytes.
x ’10’ = FIFO size is 64 bytes.
x ’11’ = FIFO size is 128 bytes.
Bits [3:2]: Reserved
Bits [5:4]: RX trigger level
x ’00’ = RX trigger level is 1, 4, 8, 14 (See Table 13 ’Receive FIFO Trigger Level Selection’).
x ’01’ = RX trigger level is 2, 8, 16, 28 (See Table 13 ’Receive FIFO Trigger Level Selection’).
x ’10’ = RX trigger level is 4, 16, 32, 56 (See Table 13 ’Receive FIFO Trigger Level Selection’).
x ’11’ = RX trigger level is 8, 32, 64, 112 (See Table 13 ’Receive FIFO Trigger Level Selection’).
Note: for Bits[5:4]= ’01’,’10’ and ’11’ make sure correct FIFO size is programmed in Bits[1:0].
24