XR28V382IL32-0A Datasheet, PDF (15/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
REV. 1.0.1
3.3V DUAL LPC UART WITH 128-BYTE FIFO
1.4.7 Internal Loopback
The V382 provides an internal loopback capability for system diagnostic purposes. The internal loopback mode
is enabled by setting MCR register bit-4 to logic 1. Figure 8 shows how the modem port signals are re-
configured. Transmit data from the transmit shift register output is internally routed to the receive shift register
input allowing the system to receive the same data that it was sending. The TX pin is held HIGH or mark
condition while RTS# and DTR# are de-asserted, and CTS#, DSR# CD# and RI# inputs are ignored. Caution:
the RX input must be held HIGH during loopback test else upon exiting the loopback test the UART may detect
and report a false “break” signal.
FIGURE 8. INTERNAL LOOPBACK
Transm it Shift R egister
(THR/FIFO )
VCC
M C R bit-4=1
R eceive Shift R egister
(RHR/FIFO )
VCC
RTS#
CTS#
DTR#
VCC
DSR#
R I#
OP1#
CD#
OP2#
TX
RX
RTS#
CTS#
DTR#
DSR#
R I#
CD#
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