XR28V382IL32-0A Datasheet, PDF (33/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
REV. 1.0.1
3.3V DUAL LPC UART WITH 128-BYTE FIFO
LCR[7]: Baud Rate Divisors Enable
Baud rate generator divisor (DLL/DLM) enable.
x Logic 0 = Data registers are selected (default).
x Logic 1 = Divisor latch registers are selected.
2.2.1.7 Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
x Logic 0 = Force DTR# output HIGH (default).
x Logic 1 = Force DTR# output LOW.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
x Logic 0 = Force RTS# output HIGH (default).
x Logic 1 = Force RTS# output LOW.
MCR[2]: Reserved
OP1# is not available as an output pin on the V382. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: Enable interrupts on SERIRQ / OP2#
Enable or disable Interrupt outputs.
x Logic 0 = Interrupts will not appear on SERIRQ pin.
x Logic 1 = If enabled in IER, interrupting condition will appear on SERIRQ pin.
In internal loopback mode (MCR[4] = ’1’), this bit controls the OP2# signal. See ’Section 1.4.7, Internal
Loopback’.
MCR[4]: Internal Loopback Enable
x Logic 0 = Disable loopback mode (default).
x Logic 1 = Enable local loopback mode, see loopback section and Figure 8.
MCR[7:5]: Reserved
2.2.1.8 Line Status Register (LSR) - Read-Only
The LSR provides the status of data transfers between the UART and the host. If IER bit-2 is enabled, LSR bit-
1 will generate an interrupt immediately and LSR bits 2-4 will generate an interrupt when a character with an
error is in the RHR.
LSR[0]: Receive Data Ready Indicator
x Logic 0 = No data in receive holding register or FIFO (default).
x Logic 1 = Data has been received and is saved in the receive holding register or FIFO.
33