XR28V382IL32-0A Datasheet, PDF (26/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
3.3V DUAL LPC UART WITH 128-BYTE FIFO
REV. 1.0.1
Bits [2:1]: WDT Interval
x ’00’ = Timer unit is 10 ms.
x ’01’ = Timer unit is 1 second.
x ’10’ = Timer unit is 1 minute.
x ’11’ = Reserved.
Bits [7:3]: Reserved
2.1.2.2.5
WDT Count Register - Read/Write
This register programs the count value for watchdog timer.
Bits [7:0]: Sets count value for watchdog timer
Writing a non-zero value to this register once will disable the timer and writing the same value again will
enable the timer. After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this byte will be set
to 0x0A. Otherwise, this byte will be set to 0x00. See Table 1 ’UART Power On Configuration’.
2.2 UART Internal Registers
The UART register set for the V382 is shown in Table 10 and Table 11.
TABLE 10: UART INTERNAL REGISTERS
OFFSET
ADDRESSES
REGISTER
RESET STATE
16C550 COMPATIBLE REGISTERS
0x0
DLL - Divisor LSB Register
0x01
0x1
DLM - Divisor MSB Register
0x00
0x0
RHR - Receive Holding Register
THR - Transmit Holding Register
0xXX
0xXX
0x1
IER - Interrupt Enable Register
0x00
0x2
ISR - Interrupt Status Register
FCR - FIFO Control Register
0x01
0x00
0x3
LCR - Line Control Register
0x00
0x4
MCR - Modem Control Register
0x00
0x5
LSR - Line Status Register
0x60
0x6
MSR - Modem Status Register
Bits 3:0 = 0
Bts 7-4 = Logic
Levels of the inputs
inverted
0x7
SPR - Scratch Pad Register
0x00
COMMENTS
LCR[7] = 1
LCR[7] = 0
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