XR28V382IL32-0A Datasheet, PDF (31/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
REV. 1.0.1
3.3V DUAL LPC UART WITH 128-BYTE FIFO
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1).
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 13 shows the complete selections.
TABLE 13: RECEIVE FIFO TRIGGER LEVEL SELECTION
FIFO MODE SELECT REGISTER
BIT-5
BIT-4
FCR BIT-7
FCR BIT-6
RECEIVE TRIGGER LEVEL
0
0
0
1
0
0
1
0
1
1
1 (default)
4
8
14
0
0
2
0
1
0
1
8
1
0
16
1
1
28
0
0
4
0
1
16
1
0
1
0
32
1
1
56
0
0
8
0
1
32
1
1
1
0
64
1
1
112
2.2.1.6 Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
0
0
1
1
BIT-0
0
1
0
1
WORD LENGTH
5 (default)
6
7
8
31