XR28V382IL32-0A Datasheet, PDF (29/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
REV. 1.0.1
3.3V DUAL LPC UART WITH 128-BYTE FIFO
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when an
overrun occurs. LSR bits 2-4 generate an interrupt when the character in the RHR has an error.
x Logic 0 = Disable the receiver line status interrupt (default).
x Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
x Logic 0 = Disable the modem status register interrupt (default).
x Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
2.2.1.4 Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 12, shows the data values (bit 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
2.2.1.4.1
Interrupt Generation:
x LSR is by any of the LSR bits 1, 2, 3 and 4.
x RXRDY Data Ready is by RX trigger level.
x RXRDY Data Time-out is by a 4-char plus 12 bits delay timer.
x TXRDY is by TX FIFO empty.
x MSR is by any of the MSR bits 0, 1, 2 and 3.
2.2.1.4.2
Interrupt Clearing:
x LSR interrupt is cleared by a read to the LSR register.
x RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
x RXRDY Time-out interrupt is cleared by reading RHR.
x TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
x MSR interrupt is cleared by a read to the MSR register.
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TABLE 12: INTERRUPT SOURCE AND PRIORITY LEVEL
PRIORITY
ISR REGISTER STATUS BITS
SOURCE OF INTERRUPT
LEVEL
BIT-3
BIT-2
BIT-1
BIT-0
1
0
1
1
0
LSR (Receiver Line Status Register)
2
1
1
0
0
RXRDY (Receive Data Time-out)
3
0
1
0
0
RXRDY (Received Data Ready)
4
0
0
1
0
TXRDY (Transmit Ready)
5
0
0
0
0
MSR (Modem Status Register)
-
0
0
0
1
None (default)
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