XR28V382IL32-0A Datasheet, PDF (25/39 Pages) Exar Corporation – 3.3V DUAL LPC UART WITH 128-BYTE FIFO

XR28V382
REV. 1.0.1
3.3V DUAL LPC UART WITH 128-BYTE FIFO
Bit [6]: Reserved
Bit [7]: TX holding register (THR) empty delay
x Logic 0 = No delay for THR empty interrupt (default).
x Logic 1 = Delay 1 transmission clock for THR empty interrupt.
2.1.2.2 Watchdog Timer Registers (LDN = 0x08)
2.1.2.2.1
WDT Enable Register - Read/Write
Bit [0]: WDT Enable/Disable
x Logic 0 = Disable the Watchdog Timer.
x Logic 1 = Enable the Watchdog Timer.
After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this bit will be set to ’1’. Otherwise,
this bit will be set to ’0’. See Table 1 ’UART Power On Configuration’.
Bits [7:1]: Reserved
2.1.2.2.2
WDT Base Address High/Low Register - Read/Write
This register indicates the MSB/LSB of watchdog timer base address.
Bits [7:0]: The MSB of watchdog timer base address (0x60).
After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this byte will be set to 0x04.
Otherwise, this bit will be set to 0x00. See Table 1 ’UART Power On Configuration’.
Bits [7:0]: The LSB of watchdog timer base address (0x61) .
After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this byte will be set to 0x42.
Otherwise, this byte will be set to 0x0. See Table 1 ’UART Power On Configuration’.
2.1.2.2.3
WDT IRQ Channel Select Register - Read/Write
This register enables / disables an interrupt request output from the watchdog timer.
Bits [3:0]: Select the IRQ channel for watchdog timer
After power on or reset, if the pin WDTOUT#/PS_WDT is sampled HIGH, this byte will be set to 0x00.
Otherwise, this byte will be set to 0x0. See Table 1 ’UART Power On Configuration’.
Bit [4]: Enable/Disable the watchdog timer IRQ
x Logic 0 = Disable the watchdog timer IRQ (default).
x Logic 1 = Enable the watchdog timer IRQ.
Bits [7:5]: Reserved
2.1.2.2.4
WDT Timer Status and Control Register - Read/Write
This register sets timer status and control timer events.
Bit [0]: Time Out Events
x Logic 0 = No time out occurred (default).
x Logic 1 = Time out occurred. Write ’1’ to this bit will clear the status.
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