XR16C854 Datasheet, PDF (9/51 Pages) Exar Corporation – QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO

XR16C854
SYMBOL DESCRIPTION
Symbol
R/-W
-RXRDY
-RXRDY A-B
-RXRDY C-D
-TXRDY
Pin
Signal
68 100 64 type
Pin Description
18 15
-
I Read/Write Strobe (active low) - This function is associated
with the 68 mode only. This pin provides the combined
functions for Read or Write strobes. A logic 1 to 0 transition
transfers the contents of the CPU data bus (D0-D7) to the
register selected by -CS and A0-A4. Similarly a logic 0 to 1
transition places the contents of a 854 register selected by
-CS and A0-A4 on the data bus, D0-D7, for transfer to an
external CPU.
38 44
-
O Receive Ready (active low) - This function is associated
with 68 and 100 pin packages only. -RXRDY contains the
wire “OR-ed” status of all four receive channel FIFO’s,
RXRDY A-D. A logic 0 indicates receive data ready status,
i.e. the RHR is full or the FIFO has one or more RX
characters available for unloading. This pin goes to a logic
1 when the FIFO/RHR is full or when there are no more
characters available in either the FIFO or RHR. The 100 pin
chip-sets provide both the combined wire “or’ed” output and
individual channel RXRDY-A-D outputs. RXRDY A-D is
discussed in a following paragraph. For 64/68 pin packages,
individual channel RX status is read by examining indi-
vidual internal registers via -CS and A0-A4 pin functions.
- 100,31
- 50,82 -
O Receive Ready A-D (active low) - This function is associ-
ated with 100 pin packages only. This function provides the
RX FIFO/RHR status for individual receive channels (A-D).
A logic 0 indicates there is receive data to read/unload, i.e.,
receive ready status with one or more RX characters
available in the FIFO/RHR. This pin is a logic 1 when the
FIFO/RHR is empty or when the programmed trigger level
has not been reached.
39 45
-
O (active low) - This function is associated with 68 and 100 pin
packages only. -TXRDY contains the wire “OR-ed” status of
all four transmit channel FIFO’s, TXRDY A-D. A logic 0
indicates a buffer ready status, i.e., at least one location is
empty and available in one of the TX channels (A-D). This
pin goes to a logic 1 when all four channels have no more
empty locations in the TX FIFO or THR. The 100 pin chip-
Rev. 1.00P
9