XR16C854 Datasheet, PDF (15/51 Pages) Exar Corporation – QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO

XR16C854
Table 4, INTERNAL REGISTER DECODE
A2 A1 A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Receive Holding Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *2
0
0
0
0
0
1
LSB of Divisor Latch
MSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Register Set (EFR, Xon/off 1-2): Note *3
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
1
1
FIFO Trigger Register
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
FIFO trigger counter
Feature Control Register
Enhanced Feature Register
Xon-1 Word
Xon-2 Word
Xoff-1 Word
Xoff-2 Word
FIFO Ready Register: Note *4
X
X
X
RXRDY (A-D), TXRDY (A-D)
Note *2: These registers are accessible only when LCR bit-7 is set to a logic 1.
Note *3: Enhanced Feature Register, Xon 1,2 and Xoff 1,2 are accessible only when the LCR is set to
“BF(HEX).
Note *4: FIFO Ready Register is available through the CSRDY interface pin only.
Rev. 1.00P
15