XR16C854 Datasheet, PDF (28/51 Pages) Exar Corporation – QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO

XR16C854
FCR BIT 6-7: (logic 0 or cleared is the default condi-
tion, RX trigger level =8)
These bits are used to set the trigger level for the
receiver FIFO interrupt. The FCTR Bits 4-5 selects
one of the following table.
TRIGGER TABLE-A (Receive)
“Default setting after reset ST16C550 mode”
BIT-7 BIT-6
FIFO trigger level
0
0
1
0
1
4
1
0
8
1
1
14
Interrupt Status Register (ISR)
The 854 provides six levels of prioritized interrupts to
minimize external software interaction. The Interrupt
Status Register (ISR) provides the user with six inter-
rupt status bits. Performing a read cycle on the ISR will
provide the user with the highest pending interrupt
level to be serviced. No other interrupts are acknowl-
edged until the pending interrupt is serviced. When-
ever the interrupt status register is read, the interrupt
status is cleared. However it should be noted that only
the current pending interrupt is cleared by the read. A
lower level interrupt may be seen after rereading the
interrupt status bits. The Interrupt Source Table 7
(below) shows the data values (bit 0-5) for the six
prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels:
TRIGGER TABLE-B (Receive)
BIT-7 BIT-6
FIFO trigger level
0
0
8
0
1
16
1
0
24
1
1
28
TRIGGER TABLE-C (Receive)
BIT-7 BIT-6
FIFO trigger level
0
0
8
0
1
16
1
0
56
1
1
60
TRIGGER TABLE-D (Receive)
BIT-7 BIT-6
FIFO trigger level
X
X
User programmable
Trigger levels
Rev. 1.00P
28