XR16C854 Datasheet, PDF (23/51 Pages) Exar Corporation – QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO

XR16C854
REGISTER FUNCTIONAL DESCRIPTIONS
The following table delineates the assigned bit functions for the fifteen 854 internal registers. The assigned
bit functions are more fully defined in the following paragraphs.
XR16C854 ACCESSIBLE REGISTERS
A2 A1 A0
Register
[Default]
Note *5
BIT-7
General Register Set
0 0 0 RHR [XX]
bit-7
000
THR [XX]
bit-7
001
IER [00]
0/
-CTS
interrupt
BIT-6
bit-6
bit-6
0/
-RTS
interrupt
010
010
011
100
101
110
FCR [00]
ISR [01]
LCR [00]
MCR [00]
LSR [60]
MSR [X0]
RCVR
trigger
(MSB)
0/
FIFO’s
enabled
divisor
latch
enable
Clock
select
0/
FIFO
error
-CD
RCVR
trigger
(LSB)
0/
FIFO’s
enabled
set
break
0/
IRRT
enable
trans.
empty
-RI
1 1 1 SCPAD [FF]
bit-7
Special Register Set Note *2
000
DLL [XX]
bit-7
0 0 1 DLM [XX]
bit-15
bit-6
bit-6
bit-14
BIT-5
bit-5
bit-5
0/
Xoff
interrupt
0/TX
trigger
(MSB)
0/
-RTS,
-CTS
set
parity
0/
Xon
Any
trans.
holding
empty
-DSR
bit-5
bit-5
bit-13
BIT-4
bit-4
bit-4
0/
Sleep
mode
0/TX
trigger
(LSB)
0/
Xoff
even
parity
loop
back
break
interrupt
-CTS
bit-4
bit-4
bit-12
BIT-3
bit-3
bit-3
modem
status
interrupt
DMA
mode
select
int
priority
bit-2
parity
enable
-OP2
framing
error
delta
-CD
bit-3
bit-3
bit-11
BIT-2
bit-2
bit-2
receive
line
status
interrupt
XMIT
FIFO
reset
int
priority
bit-1
stop
bits
-OP1
parity
error
delta
-RI
bit-2
bit-2
bit-10
BIT-1
bit-1
bit-1
transmit
holding
register
RCVR
FIFO
reset
int
priority
bit-0
word
length
bit-1
-RTS
overrun
error
delta
-DSR
bit-1
bit-1
bit-9
BIT-0
bit-0
bit-0
receive
holding
register
FIFO
enable
int
status
word
length
bit-0
-DTR
receive
data
ready
delta
-CTS
bit-0
bit-0
bit-8
Rev. 1.00P
23