XR16C854 Datasheet, PDF (34/51 Pages) Exar Corporation – QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO

XR16C854
hardware flow control. -RTS functions normally when
hardware flow control is disabled.
0 = Automatic RTS flow control is disabled. (normal
default condition)
1 = Enable Automatic RTS flow control.
EFR bit-7:
Automatic CTS Flow Control.
Logic 0 = Automatic CTS flow control is disabled.
(normal default condition)
Logic 1 = Enable Automatic CTS flow control. Trans-
mission will stop when -CTS goes to a logical 1.
Transmission will resume when the -CTS pin returns
to a logical 0.
FIFO READY REGISTER
This register is applicable to 100 pin XR16C854s only.
The FIFO resister provides the real time status of the
transmit and receive FIFO’s. Each TX and RX cannel
(A-D) has its own 128 byte FIFO. When any of the
eight TX/RX FIFO’s become full, a bit associated with
its TX/RX function and channel A-D is set in the FIFO
status register.
FIFO channel A-D RDY Bit 0-3:
0 = The transmit FIFO A-D associated with this bit is
full. This channel will not accept any more transmit
data.
1 = One or more empty locations exist in the FIFO.
FIFORdy Bit 4-7:
0 = The receive FIFO is above the programmed
trigger level or time-out is occurred.
1 = Receiver is ready and is below the programmed
trigger level.
FEATURE CONTROL REGISTER
This register controls the XR16C854 new functions
that are not available on ST16C550 or ST16C650.
FCTR BIT 0-1:
User selectable -RTS delay timer for hardware flow
control application. After reset, these bits are set to “0”
to select the next trigger level for hardware flow
control.
FCTR FCTR
Bit-1 Bit-0
0
0
0
1
1
0
1
1
Trigger
level
Next trigger
level
4 word+trigger level
6 word+trigger level
8 word+trigger level
FCTR BIT-2:
0 = Select RX input as encoded IrDa data.
1 = Select RX input as active high encoded IrDa data.
FCTR BIT-3:
Interrupt type select.
0 = Standard ST16C550 mode. Transmitter generates
interrupt when transmit holding register is empty and
transmit shift register is shifting data out.
1 = Transmit empty interrupt. Transmit interrupt is
generated when transmit holding and shift register is
empty.
FCTR BIT 4-5:
Transmit / receive trigger table select.
FCTR
Bit-5
0
0
1
1
FCTR
Bit-4
Table
0
Table-A (TX/RX)
1
Table-B (TX/RX)
0
Table-C (TX/RX)
1
Table-D (TX/RX)
FCTR BIT-6:
Register mode select.
0 = Scratch Pad register is selected as general read
and write register. ST16C550 compatible mode.
1 = FIFO count register, Enhanced Mode Select
Register. Number of characters in transmit or receive
holding register can be read via scratch pad register
when this bit is set. Enhanced Mode is selected when
it is written into it.
Rev. 1.00P
34