XR16C854 Datasheet, PDF (11/51 Pages) Exar Corporation – QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO

XR16C854
SYMBOL DESCRIPTION
Symbol
-DSR A-B
-DSR C-D
-DTR A-B
-DTR C-D
-RI A-B
-RI C-D
-RTS A-B
-RTS C-D
Pin
Signal
68 100 64 type
Pin Description
MSR bit-4. This pin only affects the transmit and receive
operations when Auto CTS function is enabled via the
Enhanced Feature Register (EFR) bit-7, for hardware flow
control operation.
10,26 7,23 1,17
44,60 58,74 32,48 I Data Set Ready (active low) - These inputs are associated
with individual UART channels, A through D. A logic 0 on
this pin indicates the modem or data set is powered-on and
is ready for data exchange with the UART. This pin has no
effect on the UART’s transmit or receive operation.
12,24 9,21 3,15
46,58 60,72 34,46 O Data Terminal Ready (active low) - These inputs are
associated with individual UART channels, A through D. A
logic 0 on this pin indicates that the 854 is powered-on and
ready. This pin can be controlled via the modem control
register. Writing a logic 1 to MCR bit-0 will set the -DTR
output to logic 0, enabling the modem. This pin will be a logic
1 after writing a logic 0 to MCR bit-0, or after a reset. This
pin has no effect on the UART’s transmit or receive opera-
tion.
8,28 98,33 63,19
42,62 48,84 30,50 I Ring Indicator (active low) - These inputs are associated
with individual UART channels, A through D. A logic 0 on
this pin indicates the modem has received a ringing signal
from the telephone line. A logic 1 transition on this input pin
will generate an interrupt.
14,22 11,19 5,13
48,56 62,70 36,44 O Request to Send (active low) - These outputs are associated
with individual UART channels, A through D. A logic 0 on the
-RTS pin indicates the transmitter has data ready and
waiting to send. Writing a logic 1 in the modem control
register (MCR bit-1) will set this pin to a logic 0 indicating
data is available. After a reset this pin will be set to a logic
1. This pin only affects the transmit and receive operations
when Auto RTS function is enabled via the Enhanced
Feature Register (EFR) bit-6, for hardware flow control
Rev. 1.00P
11