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XR16C854 Datasheet, PDF (19/51 Pages) Exar Corporation – QUAD UART WITH RX/TX FIFO COUNTERS,128-BYTE FIFO
XR16C854
Single baud rate generator is provided for the
transmitter and receiver, allowing independent TX/
RX channel control. The programmable Baud Rate
Generator is capable of accepting an input clock up
to 24 MHz, as required for supporting a 1.5Mbps
data rate. The 854 can be configured for internal or
external clock operation. For internal clock oscilla-
tor operation, an industry standard microprocessor
crystal (parallel resonant/ 22-33 pF load) is con-
nected externally between the XTAL1 and XTAL2
pins (see figure ). Alternatively, an external clock
can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom
rates. (see Baud Rate Generator Programming).
The generator divides the input 16X clock by any
divisor from 1 to 216 -1. The 854 divides the basic
crystal or external clock by 16. Further division of this
16X clock provides two table rates to support low and
high data rate applications using the same system
design. After a hardware reset and during initializa-
tion, the 854 sets the default baud rate table according
to the state of the CLKSEL. pin. A logic 1 on CLKSEL
will set the 1X clock default whereas, logic 0 will set
the 4X clock default table. Following the default clock
rate selection during initialization, the rate tables can
be changed by the internal register, MCR bit-7. Setting
MCR bit-7 to a logic 1 when CLKSEL is a logic 1
provides an additional divide by 4 whereas, setting
MCR bit-7 to a logic 0 only divides by 1. (See Table 5
and Figure 11). Customized Baud Rates can be
achieved by selecting the proper divisor values for the
MSB and LSB sections of baud rate generator.
Programming the Baud Rate Generator Registers
DLM (MSB) and DLL (LSB) provides a user capability
for selecting the desired final baud rate. The example
in Table 5 below, shows the two selectable baud rate
tables available when using a 7.3728 MHz crystal.
Table 5, BAUD RATE GENERATOR PROGRAMMING TABLE (7.3728 MHz CLOCK):
Output
Baud Rate
MCR
BIT-7=1
Output
Baud Rate
MCR
Bit-7=0
User
16 x Clock
Divisor
(Decimal)
User
16 x Clock
Divisor
(HEX)
DLM
Program
Value
(HEX)
50
200
2304
900
09
300
1200
384
180
01
600
2400
192
C0
00
1200
4800
96
60
00
2400
9600
48
30
00
4800
19.2K
24
18
00
9600
38.4k
12
0C
00
19.2k
76.8k
6
06
00
38.4k
153.6k
3
03
00
57.6k
230.4k
2
02
00
115.2k
460.8k
1
01
00
DLL
Program
Value
(HEX)
00
80
C0
60
30
18
0C
06
03
02
01
Rev. 1.00P
19